EPM7128AETI100-7N vs EPM7128AETI100-7 对比
详细并排对比 EPM7128AETI100-7N 出自 Altera 和 EPM7128AETI100-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteAltera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 Obsolete规格对比
| 参数 | EPM7128AETI100-7N | EPM7128AETI100-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $28.50 | $30.10 |
| Series | MAX 7000A | — |
| Family | MAX 7000A CPLD | MAX 7000A |
| Macro Cells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 84 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD max) | 7 ns | — |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Process Technology | CMOS EEPROM | — |
| 封装 | 100-pin TQFP (14x14 mm) | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | -40C to +85C (Industrial) | -40 C to +85 C (Industrial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| RoHS 状态 | Compliant | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| User I/Os | — | 84 |
| Logic Blocks (LABs) | — | 8 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | — | 4 dedicated |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |