EPM7128AETI100-7N vs EPM7128AETI100-7 Comparaison
Comparaison détaillée côte à côte de EPM7128AETI100-7N par Altera et EPM7128AETI100-7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteAltera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteComparaison des spécifications
| Paramètre | EPM7128AETI100-7N | EPM7128AETI100-7 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,50 | $30,10 |
| Series | MAX 7000A | — |
| Family | MAX 7000A CPLD | MAX 7000A |
| Macro Cells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 84 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD max) | 7 ns | — |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Process Technology | CMOS EEPROM | — |
| Boîtier | 100-pin TQFP (14x14 mm) | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | -40C to +85C (Industrial) | -40 C to +85 C (Industrial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| User I/Os | — | 84 |
| Logic Blocks (LABs) | — | 8 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | — | 4 dedicated |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |