EPM7128AETI100-7N vs EPM7128AETI100-7 Comparison

Detailed side-by-side comparison of EPM7128AETI100-7N by Altera and EPM7128AETI100-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128AETI100-7N EPM7128AETI100-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Series MAX 7000A —
Family MAX 7000A CPLD MAX 7000A
Macro Cells 128 —
Number of Usable Gates 2,500 —
Number of I/O 84 —
Number of Logic Array Blocks (LABs) 8 —
Propagation Delay (tPD max) 7 ns —
Maximum Operating Frequency (fCNT) 129.9 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V —
I/O Bank Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) —
Process Technology CMOS EEPROM —
Package 100-pin TQFP (14x14 mm) 100-pin TQFP (1.0 mm pitch, 14 x 14 mm)
Mounting Type Surface Mount Surface Mount
Operating Temperature -40C to +85C (Industrial) -40 C to +85 C (Industrial)
In-System Programmability Yes (JTAG IEEE 1149.1) —
RoHS Status Compliant [DATA_NEEDED: confirm RoHS for non-N suffix]
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 128
Usable Gates — 2,500
User I/Os — 84
Logic Blocks (LABs) — 8
Pin-to-Pin Delay (tPD) — 7.5 ns
Maximum Counter Frequency — 129.9 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Bank Supply (VCCIO) — 2.5 V / 3.3 V / 5 V (MultiVolt)
Configuration Memory — EEPROM (non-volatile, in-system programmable)
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
Global Clock Inputs — 4 dedicated
Lead-Free Version (MPN Suffix) — -N suffix denotes lead-free (e.g., EPM7128AETI100-7N)

Datasheets & Resources

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