EPM7128SQC160-15N vs EPM7128SQC100-15 对比

详细并排对比 EPM7128SQC160-15N 出自 Intel 和 EPM7128SQC100-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ 最后一次采购

规格对比

参数 EPM7128SQC160-15N EPM7128SQC100-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $23.00 $8.20
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000 MAX 7000
Macro Cells 128 —
Logic Array Blocks (LABs) 8 4 (16 macrocells each)
User I/O Count 100 —
Usable Gates 2.5K —
Propagation Delay (tPD) 15 ns —
Maximum Internal Frequency 76.9 MHz —
Supply Voltage (VCCINT) 5 V 5 V (5% tolerance)
I/O Voltage Tolerance 3.3 V / 5 V mixed —
Programming Technology EEPROM (non-volatile) EEPROM (in-system programmable via JTAG)
In-System Programmability Yes (JTAG-compatible) —
封装 160-pin PQFP / BQFP (Plastic Quad Flat Pack) 100-pin PQFP (Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
工作温度 0°C to +70°C (commercial) 0C to +70C (Commercial)
RoHS 状态 [DATA_NEEDED: RoHS status] Non-compliant (SnPb lead finish - legacy PQFP)
Lead-Free [DATA_NEEDED: lead-free status] —
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 128
User I/Os — 84
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX value]
Typical Gate Count — 2,500 gates
JTAG Interface — IEEE Std. 1149.1 compliant
MSL 等级 — 3 (168 hours)

数据手册与资源

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