EPM7128STC100-6 vs EPM7128STC100-6N 对比

详细并排对比 EPM7128STC100-6 出自 Intel 和 EPM7128STC100-6N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128STC100-6 EPM7128STC100-6N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $5.20 $10.50
Family MAX 7000S MAX 7000S
Macrocells 128 —
Equivalent Gates 2,500 —
User I/O Pins 84 —
Pin-to-Pin Delay (tPD) 6 ns —
Maximum Internal Frequency (fCNT) 147.1 MHz —
Supply Voltage (VCCINT / VCCIO) 5 V —
封装 100-pin TQFP (STC100) —
安装类型 Surface Mount Surface Mount
Programming Interface JTAG (IEEE Std. 1149.1) / ISP —
工作温度 0C to +70C (commercial) 0C to +70C (Commercial)
PCI Compliance 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) —
Lead Pitch 1.0 mm (TQFP) —
Lead-Free / RoHS Contains lead (non-RoHS original; -6N variant is lead-free) —
Configuration Memory On-chip EEPROM (non-volatile) —
Usable Gates — 2,500
Macro Cells — 128
User I/Os — 84
Logic Family — CMOS
引脚数 — 100
Package Type — TQFP-100
Maximum Internal Frequency — 147.1 MHz
Internal Counter Frequency — 250 MHz
Propagation Delay (tPD) — 6 ns
Pin-to-Pin Delay — 4.5 ns
Supply Voltage (VCCIO) — 5 V
Process Technology — CMOS EEPROM
Programmability — In-System Programmable (ISP) via JTAG
JTAG Support — IEEE 1149.1 Boundary Scan
RoHS 状态 — Non-Compliant (lead-bearing package)

数据手册与资源

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