EPM7256BQC208-7 - 256-Macro MAX 7000B CPLD, 208-PQFP | Intel
料号： EPM7256BQC208-7 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPM7256BQC208-7 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that sits between discrete 74-series glue logic and larger FPGAs. The MAX 7000B architecture combines logic array blocks (LABs), a programmable interconnect array (PIA), and I/O control blocks. Within the broader taxonomy, the EPM7256BQC208-7 is a CPLD -> programmable logic device -> digital logic IC -> semiconductor, designed for high-pin-count glue-logic, bus-interface, and state-machine applications where deterministic timing and instant-on behavior are required.
Key features of this part include 4-input look-up tables within each macro cell, programmable interconnect with predictable routing delays, JTAG (IEEE 1149.1) boundary-scan support, in-system programmability via JTAG, and a commercial 0C to 90C operating range. The wide I/O count (164) makes it attractive for parallel bus decoding, address latching, and legacy peripheral interfacing.
Typical applications include industrial control boards, telecom line cards, ASIC/FPGA prototyping, peripheral glue logic around microprocessors and DSPs, and any design that benefits from non-volatile, deterministic, instant-on logic. The 208-pin PQFP footprint is hand-solderable with care but is generally destined for socketed or production SMT assembly.
直接替换替代料： EPM7256BQC208-7 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM7256BQC208-7 （相同外形与封装尺寸） ——差异在于 Package, RoHS Status, Family, In-System Programmability, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
EPM7256BQC208-10
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EPM7256BQI208-7
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EPM7256AQC208-7
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$27.2 / 个
查看数据手册 →EPM7256AQI208-10
✅ 直接替换✓ 有现货
$13.22 / 个
查看数据手册 →EPM7256BQC208-7 最大额定值与电气特性
| Family | MAX 7000B |
| Device Type | CPLD - Complex Programmable Logic Device |
| Usable Gates | 5,000 |
| Macro Cells | 256 |
| User I/Os | 164 |
| Logic Elements / LABs | 16 Logic Array Blocks |
| Maximum Internal Frequency | 126.6 MHz |
| Propagation Delay (tPD) | 7.5 ns (-7 speed grade) |
| Core Supply Voltage | 2.5 V |
| 工作温度 | 0C to +90C (commercial) |
| 封装 | 208-pin PQFP |
| 安装类型 | Surface Mount |
| Configuration Memory | Non-volatile EEPROM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
| In-System Programmability | Yes (via JTAG) |
| RoHS 状态 | Compliant per distributor listings |
EPM7256BQC208-7 引脚配置
| 引脚 1 | GND — Ground |
| 引脚 2 | I/O — User I/O pin (bank 1) |
| 引脚 3 | I/O — User I/O pin (bank 1) |
| 引脚 4 | I/O — User I/O pin (bank 1) |
| 引脚 5 | I/O — User I/O pin (bank 1) |
| 引脚 6 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 7 | I/O — User I/O pin (bank 2) |
| 引脚 8 | I/O — User I/O pin (bank 2) |
| 引脚 9 | I/O — User I/O pin (bank 2) |
| 引脚 10 | I/O — User I/O pin (bank 2) |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — User I/O pin (bank 2) |
| 引脚 13 | I/O — User I/O pin (bank 2) |
| 引脚 14 | I/O — User I/O pin (bank 2) |
| 引脚 15 | I/O — User I/O pin (bank 2) |
| 引脚 16 | VCCIO1 — I/O bank 1 reference voltage |
| 引脚 17 | TDI — JTAG Test Data In |
| 引脚 18 | TMS — JTAG Test Mode Select |
| 引脚 19 | TCK — JTAG Test Clock |
| 引脚 20 | GND — Ground |
| 引脚 21 | I/O — User I/O pin (bank 1) |
| 引脚 22 | I/O — User I/O pin (bank 1) |
| 引脚 23 | I/O — User I/O pin (bank 1) |
| 引脚 24 | I/O — User I/O pin (bank 1) |
| 引脚 25 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 26 | I/O — User I/O pin (bank 3) |
| 引脚 27 | I/O — User I/O pin (bank 3) |
| 引脚 28 | I/O — User I/O pin (bank 3) |
| 引脚 29 | I/O — User I/O pin (bank 3) |
| 引脚 30 | GND — Ground |
| 引脚 31 | I/O — User I/O pin (bank 3) |
| 引脚 32 | I/O — User I/O pin (bank 3) |
| 引脚 33 | I/O — User I/O pin (bank 3) |
| 引脚 34 | I/O — User I/O pin (bank 3) |
| 引脚 35 | VCCIO3 — I/O bank 3 reference voltage |
| 引脚 36 | I/O — User I/O pin (bank 4) |
| 引脚 37 | I/O — User I/O pin (bank 4) |
| 引脚 38 | I/O — User I/O pin (bank 4) |
| 引脚 39 | I/O — User I/O pin (bank 4) |
| 引脚 40 | GND — Ground |
| 引脚 41 | I/O — User I/O pin (bank 4) |
| 引脚 42 | I/O — User I/O pin (bank 4) |
| 引脚 43 | I/O — User I/O pin (bank 4) |
| 引脚 44 | I/O — User I/O pin (bank 4) |
| 引脚 45 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 46 | I/O — User I/O pin (bank 2) |
| 引脚 47 | I/O — User I/O pin (bank 2) |
| 引脚 48 | I/O — User I/O pin (bank 2) |
| 引脚 49 | I/O — User I/O pin (bank 2) |
| 引脚 50 | GND — Ground |
| 引脚 51 | I/O — User I/O pin (bank 2) |
| 引脚 52 | I/O — User I/O pin (bank 2) |
| 引脚 53 | I/O — User I/O pin (bank 2) |
| 引脚 54 | I/O — User I/O pin (bank 2) |
| 引脚 55 | VCCIO2 — I/O bank 2 reference voltage |
| 引脚 56 | I/O — User I/O pin (bank 1) |
| 引脚 57 | I/O — User I/O pin (bank 1) |
| 引脚 58 | I/O — User I/O pin (bank 1) |
| 引脚 59 | I/O — User I/O pin (bank 1) |
| 引脚 60 | GND — Ground |
| 引脚 61 | I/O — User I/O pin (bank 1) |
| 引脚 62 | I/O — User I/O pin (bank 1) |
| 引脚 63 | I/O — User I/O pin (bank 1) |
| 引脚 64 | I/O — User I/O pin (bank 1) |
| 引脚 65 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 66 | I/O — User I/O pin (bank 3) |
| 引脚 67 | I/O — User I/O pin (bank 3) |
| 引脚 68 | I/O — User I/O pin (bank 3) |
| 引脚 69 | I/O — User I/O pin (bank 3) |
| 引脚 70 | GND — Ground |
| 引脚 71 | I/O — User I/O pin (bank 3) |
| 引脚 72 | I/O — User I/O pin (bank 3) |
| 引脚 73 | I/O — User I/O pin (bank 3) |
| 引脚 74 | I/O — User I/O pin (bank 3) |
| 引脚 75 | VCCIO4 — I/O bank 4 reference voltage |
| 引脚 76 | I/O — User I/O pin (bank 4) |
| 引脚 77 | I/O — User I/O pin (bank 4) |
| 引脚 78 | I/O — User I/O pin (bank 4) |
| 引脚 79 | I/O — User I/O pin (bank 4) |
| 引脚 80 | GND — Ground |
| 引脚 81 | I/O — User I/O pin (bank 4) |
| 引脚 82 | I/O — User I/O pin (bank 4) |
| 引脚 83 | I/O — User I/O pin (bank 4) |
| 引脚 84 | I/O — User I/O pin (bank 4) |
| 引脚 85 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 86 | I/O — User I/O pin (bank 2) |
| 引脚 87 | I/O — User I/O pin (bank 2) |
| 引脚 88 | I/O — User I/O pin (bank 2) |
| 引脚 89 | I/O — User I/O pin (bank 2) |
| 引脚 90 | GND — Ground |
| 引脚 91 | I/O — User I/O pin (bank 2) |
| 引脚 92 | I/O — User I/O pin (bank 2) |
| 引脚 93 | I/O — User I/O pin (bank 2) |
| 引脚 94 | I/O — User I/O pin (bank 2) |
| 引脚 95 | VCCIO2 — I/O bank 2 reference voltage |
| 引脚 96 | I/O — User I/O pin (bank 1) |
| 引脚 97 | I/O — User I/O pin (bank 1) |
| 引脚 98 | I/O — User I/O pin (bank 1) |
| 引脚 99 | I/O — User I/O pin (bank 1) |
| 引脚 100 | GND — Ground |
| 引脚 101 | I/O — User I/O pin (bank 1) |
| 引脚 102 | I/O — User I/O pin (bank 1) |
| 引脚 103 | I/O — User I/O pin (bank 1) |
| 引脚 104 | I/O — User I/O pin (bank 1) |
| 引脚 105 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 106 | I/O — User I/O pin (bank 3) |
| 引脚 107 | I/O — User I/O pin (bank 3) |
| 引脚 108 | I/O — User I/O pin (bank 3) |
| 引脚 109 | I/O — User I/O pin (bank 3) |
| 引脚 110 | GND — Ground |
| 引脚 111 | I/O — User I/O pin (bank 3) |
| 引脚 112 | I/O — User I/O pin (bank 3) |
| 引脚 113 | I/O — User I/O pin (bank 3) |
| 引脚 114 | I/O — User I/O pin (bank 3) |
| 引脚 115 | VCCIO3 — I/O bank 3 reference voltage |
| 引脚 116 | I/O — User I/O pin (bank 4) |
| 引脚 117 | I/O — User I/O pin (bank 4) |
| 引脚 118 | I/O — User I/O pin (bank 4) |
| 引脚 119 | I/O — User I/O pin (bank 4) |
| 引脚 120 | GND — Ground |
| 引脚 121 | I/O — User I/O pin (bank 4) |
| 引脚 122 | I/O — User I/O pin (bank 4) |
| 引脚 123 | I/O — User I/O pin (bank 4) |
| 引脚 124 | I/O — User I/O pin (bank 4) |
| 引脚 125 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 126 | I/O — User I/O pin (bank 2) |
| 引脚 127 | I/O — User I/O pin (bank 2) |
| 引脚 128 | I/O — User I/O pin (bank 2) |
| 引脚 129 | I/O — User I/O pin (bank 2) |
| 引脚 130 | GND — Ground |
| 引脚 131 | I/O — User I/O pin (bank 2) |
| 引脚 132 | I/O — User I/O pin (bank 2) |
| 引脚 133 | I/O — User I/O pin (bank 2) |
| 引脚 134 | I/O — User I/O pin (bank 2) |
| 引脚 135 | VCCIO2 — I/O bank 2 reference voltage |
| 引脚 136 | I/O — User I/O pin (bank 1) |
| 引脚 137 | I/O — User I/O pin (bank 1) |
| 引脚 138 | I/O — User I/O pin (bank 1) |
| 引脚 139 | I/O — User I/O pin (bank 1) |
| 引脚 140 | GND — Ground |
| 引脚 141 | I/O — User I/O pin (bank 1) |
| 引脚 142 | I/O — User I/O pin (bank 1) |
| 引脚 143 | I/O — User I/O pin (bank 1) |
| 引脚 144 | I/O — User I/O pin (bank 1) |
| 引脚 145 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 146 | I/O — User I/O pin (bank 3) |
| 引脚 147 | I/O — User I/O pin (bank 3) |
| 引脚 148 | I/O — User I/O pin (bank 3) |
| 引脚 149 | I/O — User I/O pin (bank 3) |
| 引脚 150 | GND — Ground |
| 引脚 151 | I/O — User I/O pin (bank 3) |
| 引脚 152 | I/O — User I/O pin (bank 3) |
| 引脚 153 | I/O — User I/O pin (bank 3) |
| 引脚 154 | I/O — User I/O pin (bank 3) |
| 引脚 155 | VCCIO3 — I/O bank 3 reference voltage |
| 引脚 156 | I/O — User I/O pin (bank 4) |
| 引脚 157 | I/O — User I/O pin (bank 4) |
| 引脚 158 | I/O — User I/O pin (bank 4) |
| 引脚 159 | I/O — User I/O pin (bank 4) |
| 引脚 160 | GND — Ground |
| 引脚 161 | I/O — User I/O pin (bank 4) |
| 引脚 162 | I/O — User I/O pin (bank 4) |
| 引脚 163 | I/O — User I/O pin (bank 4) |
| 引脚 164 | I/O — User I/O pin (bank 4) |
| 引脚 165 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 166 | I/O — User I/O pin (bank 2) |
| 引脚 167 | I/O — User I/O pin (bank 2) |
| 引脚 168 | I/O — User I/O pin (bank 2) |
| 引脚 169 | I/O — User I/O pin (bank 2) |
| 引脚 170 | GND — Ground |
| 引脚 171 | I/O — User I/O pin (bank 2) |
| 引脚 172 | I/O — User I/O pin (bank 2) |
| 引脚 173 | I/O — User I/O pin (bank 2) |
| 引脚 174 | I/O — User I/O pin (bank 2) |
| 引脚 175 | VCCIO2 — I/O bank 2 reference voltage |
| 引脚 176 | I/O — User I/O pin (bank 1) |
| 引脚 177 | I/O — User I/O pin (bank 1) |
| 引脚 178 | I/O — User I/O pin (bank 1) |
| 引脚 179 | I/O — User I/O pin (bank 1) |
| 引脚 180 | GND — Ground |
| 引脚 181 | I/O — User I/O pin (bank 1) |
| 引脚 182 | I/O — User I/O pin (bank 1) |
| 引脚 183 | I/O — User I/O pin (bank 1) |
| 引脚 184 | I/O — User I/O pin (bank 1) |
| 引脚 185 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 186 | I/O — User I/O pin (bank 3) |
| 引脚 187 | I/O — User I/O pin (bank 3) |
| 引脚 188 | I/O — User I/O pin (bank 3) |
| 引脚 189 | I/O — User I/O pin (bank 3) |
| 引脚 190 | GND — Ground |
| 引脚 191 | I/O — User I/O pin (bank 3) |
| 引脚 192 | I/O — User I/O pin (bank 3) |
| 引脚 193 | I/O — User I/O pin (bank 3) |
| 引脚 194 | I/O — User I/O pin (bank 3) |
| 引脚 195 | VCCIO3 — I/O bank 3 reference voltage |
| 引脚 196 | I/O — User I/O pin (bank 4) |
| 引脚 197 | I/O — User I/O pin (bank 4) |
| 引脚 198 | I/O — User I/O pin (bank 4) |
| 引脚 199 | I/O — User I/O pin (bank 4) |
| 引脚 200 | GND — Ground |
| 引脚 201 | I/O — User I/O pin (bank 4) |
| 引脚 202 | I/O — User I/O pin (bank 4) |
| 引脚 203 | I/O — User I/O pin (bank 4) |
| 引脚 204 | I/O — User I/O pin (bank 4) |
| 引脚 205 | VCCINT — Core supply voltage, 2.5 V |
| 引脚 206 | TDO — JTAG Test Data Out |
| 引脚 207 | DEV_CLRn — Device clear (active low) |
| 引脚 208 | DEV_OE — Device output enable |
典型应用
EPM7256BQC208-7 适用于 6 应用s: Industrial Control Glue Logic, Telecom Line-Card Interface, ASIC and FPGA Prototyping, Legacy Peripheral Glue Logic, Automotive Infotainment Bus Bridge, Test and Measurement Instrumentation.
Industrial Control Glue Logic
The EPM7256BQC208-7 is widely used in industrial PLCs and motor-control boards where 164 user I/Os and deterministic 7.5 ns tPD propagation delay let designers replace dozens of 74-series glue-logic chips with one programmable device. The non-volatile EEPROM configuration retains state through brown-outs and power cycling, which is critical for industrial equipment that must resume operation without re-flashing. The 2.5 V core with 5 V-tolerant I/O banks (via VCCIO) allows direct interfacing with legacy 5 V peripherals, optocouplers, and 24 V industrial sensors. Engineers value the JTAG in-system programmability for firmware updates on deployed equipment.
推荐
Telecom Line-Card Interface
Telecom line cards frequently use the EPM7256BQC208-7 to perform bus arbitration, address decoding, and protocol translation between network processors and TDM/Ethernet framer ASICs. The 126.6 MHz internal frequency supports high-speed glue functions between Fast Ethernet PHYs, T1/E1 framers, and backplane buses. The deterministic timing of CPLD logic (versus FPGA soft cores) simplifies timing closure for telecom applications where jitter budgets are tight. The 208-pin PQFP package is large enough to break out 164 I/Os into multiple parallel data buses without requiring additional bus transceivers.
推荐
ASIC and FPGA Prototyping
Designers prototyping ASICs or validating FPGA-based designs use the EPM7256BQC208-7 as a hardware emulator for glue logic that will eventually be absorbed into an ASIC. The 256 macro cells and 5,000 usable gates are sufficient to model medium-complexity state machines, FIFO controllers, and custom bus protocols. The non-volatile EEPROM lets prototype boards boot immediately without external boot PROMs, accelerating bring-up and bench testing. Quartus II design entry with schematic capture and Verilog/VHDL synthesis reduces design iteration time versus discrete TTL prototypes.
推荐
Legacy Peripheral Glue Logic
The EPM7256BQC208-7 replaces 74HC/74FCT glue logic around microprocessors, DSPs, and memory interfaces. Typical uses include address decoding, chip-select generation, wait-state insertion, and interrupt prioritization. The 164 I/Os accommodate parallel SRAM, NOR flash, and peripheral interfaces simultaneously, eliminating the need for separate address-latch and decoder chips. Programmable pin assignments simplify PCB routing when designers need to swap signals between board revisions without re-spinning the layout.
推荐
Automotive Infotainment Bus Bridge
In automotive infotainment systems the EPM7256BQC208-7 bridges between I2S audio buses, SPI peripherals, and CAN/LIN network segments. The MAX 7000B architecture supports 5 V-tolerant I/O banks for direct connection to legacy automotive microcontrollers and CAN transceivers. The 7.5 ns tPD keeps audio sample-rate jitter well below audible thresholds. Designers value the JTAG interface for end-of-line programming in automotive manufacturing.
推荐
Test and Measurement Instrumentation
Test equipment such as logic analyzers, oscilloscope front-ends, and protocol exercisers use the EPM7256BQC208-7 to perform pattern generation, channel multiplexing, and trigger logic. The deterministic 7.5 ns propagation delay supports precise timing-critical trigger generation, while the 164 I/Os allow parallel pattern output across 32+ channels with margin for address and control signals. The PQFP package is large enough to expose all I/Os on a daughter-card for ribbon-cable connection to a backplane test fixture.
推荐
推荐产品汇总
工程参考数据： EPM7256BQC208-7 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM7256BQC208-10 | EPM7256BQI208-7 | EPM7256AQC208-7 | EPM7256AQI208-10 |
|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 7000B | MAX 7000B | MAX 7000B | MAX 7000A | MAX 7000A |
| Macro Cells | 256 | 256 | 256 | 256 | 256 |
| Propagation Delay (tPD) | 7.5 ns (-7) | 10 ns (-10) | 7.5 ns (-7) | 7.5 ns (-7) | 10 ns (-10) |
| Core Voltage | 2.5 V | 2.5 V | 2.5 V | 3.3 V | 3.3 V |
| Operating Temperature | 0C to +90C (commercial) | 0C to +90C | -40C to +85C (industrial) | 0C to +90C | -40C to +85C (industrial) |
| User I/Os | 164 | 164 | 164 | 164 | 164 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
关键差异点
- Same PQFP-208 package and 256 macro cells as MAX 7000A, but on a 2.5 V core （对比 EPM7256AQC208-7)
- Industrial temperature option in the same PQFP-208 footprint （对比 EPM7256BQI208-7)
- Same die as EPM7256BQC208-10 with -7 speed grade for 25% faster tPD （对比 EPM7256BQC208-10)
设计说明
Estimated: at typical 50 MHz toggle activity across 100 of 164 I/Os with 5 V VCCIO, dynamic current is approximately 50-80 mA from VCCIO plus 30-50 mA from VCCINT (2.5 V). Decouple each VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, and add a 10 uF bulk capacitor per supply rail near the package. PQFP packages do not have an exposed thermal pad; use a ground pour under the device to spread heat and lower loop inductance on switching outputs.
Route JTAG signals (TDI, TDO, TMS, TCK) in a daisy-chain topology with 10K pull-ups on TMS and TCK per IEEE 1149.1. Keep JTAG traces short (<= 50 mm) and guarded by GND to avoid noise-induced programming failures. Place a 4.7K pull-up on DEV_CLRn and DEV_OE to default the device to user mode after configuration, or pull DEV_OE low to tri-state all I/Os during in-system programming.
Do not confuse the EPM7256BQC208-7 (MAX 7000B, 2.5 V core) with the EPM7256AQC208-7 (MAX 7000A, 3.3 V core). They share the same PQFP-208 footprint but require different VCCINT rails; substituting one for the other without re-routing power will damage the device. Also note that Quartus II versions earlier than 13.0 SP1 may not support the latest MAX 7000B programming algorithms - use Quartus II 13.0 SP1 or later for reliable programming file generation.
PQFP-208 leads have approximately 1.5 nH of lead inductance each, which can cause ringing on high-speed outputs above 50 MHz. For clock-like signals above 50 MHz, source-terminate with a 33-ohm series resistor to dampen reflections, and keep trace stubs < 5 mm. Place a 50-ohm characteristic-impedance reference for controlled-impedance signals routed off-device.
合规信息
RoHS and REACH compliance per distributor listings (DigiKey, Mouser, Arrow). The MAX 7000B family is not AEC-Q100 qualified; for automotive applications consider MAX II or MAX V automotive-grade variants.