EPM9320RC208-15N vs EPM9320RI208-10N 对比

详细并排对比 EPM9320RC208-15N 出自 Intel 和 EPM9320RI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N ✓ 量产中

规格对比

参数 EPM9320RC208-15N EPM9320RI208-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $0.00 $27.20
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) Complex Programmable Logic Device (CPLD)
Usable Gates 6,000 6,000
Macro Cells 320 320
Flip-Flops 484 —
Configurable I/O Lines 128 —
Propagation Delay (tPD) 15 ns —
最大时钟频率 117.6 MHz —
电源电压 5.0 V 5 V
I/O Voltage Compatibility 3.3 V or 5 V —
Configuration Technology CMOS EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes (JTAG/ISP)
封装 208-pin RQFP (PowerQuad Flat Pack) 208-pin RQFP (PowerQuad II)
Terminal Pitch 0.5 mm —
工作温度范围 0C to +70C (commercial) -40C to +85C (industrial)
安装类型 Surface Mount Surface Mount
Packaging Tray —
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant (N suffix = lead-free)
Logic Array Blocks (LABs) — 20
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Maximum System Clock Frequency — 100 MHz
I/O Voltage — 5 V
User I/O Pins — 160
Configuration Memory — EEPROM (non-volatile)
Lead Finish — Lead-free (matte tin)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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