EPM9320RC208-15N vs EPM9320RI208-10N Comparison
Detailed side-by-side comparison of EPM9320RC208-15N by Intel and EPM9320RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-15N | EPM9320RI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Active |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | Complex Programmable Logic Device (CPLD) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Flip-Flops | 484 | — |
| Configurable I/O Lines | 128 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Clock Frequency | 117.6 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Technology | CMOS EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (JTAG/ISP) |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| Terminal Pitch | 0.5 mm | — |
| Operating Temperature Range | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Logic Array Blocks (LABs) | — | 20 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Configuration Memory | — | EEPROM (non-volatile) |
| Lead Finish | — | Lead-free (matte tin) |
| MSL Level | — | [DATA_NEEDED: MSL level] |