EPM9320RC208-20N vs EPM9320RI208-20 对比

详细并排对比 EPM9320RC208-20N 出自 Altera 和 EPM9320RI208-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320RC208-20N EPM9320RI208-20
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $18.95
Device Family MAX 9000 —
Logic Type Complex Programmable Logic Device (CPLD) —
Usable Gates 6,000 6,000
Macro Cells 320 —
Logic Array Blocks 20 —
Maximum Pin-to-Pin Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz 100 MHz
电源电压 5.0 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes - IEEE 1149.1 JTAG, 5.0-V ISP
User I/O Pins 168 [DATA_NEEDED: I/O pin count for 208-pin RQFP]
封装 208-pin RQFP (PowerQuad II) 208-pin RQFP (Power Quad Flat Pack)
安装类型 Surface Mount Surface Mount
工作温度 [DATA_NEEDED: operating temperature range] —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Lead Finish [DATA_NEEDED: lead finish] —
MSL 等级 [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
Family — MAX 9000
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 320
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5.0 V
Logic Elements / LABs — 20 Logic Array Blocks (16 macro cells each)
Programmable Interconnect — Programmable Interconnect Array (PIA)
Dedicated Input Pins — 4 (low-skew global)
Operating Temperature Grade — Industrial
Technology — CMOS EEPROM

数据手册与资源

浏览全部产品 创建 BOM 获取报价