EPM9320RI208-20 - MAX 9000 CPLD, 320 Macrocells, 20ns | Intel
料号： EPM9320RI208-20 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.2 | $2,720.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $18.95 | $18,950.00 |
EPM9320RI208-20 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile, instantaneously-on programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a programmable interconnect matrix. CPLDs sit hierarchically below FPGAs in the programmable logic taxonomy, offering deterministic timing, lower power, and simpler glue-logic integration than FPGAs, while delivering far higher logic density than legacy SPLDs/PALs. They are commonly used as bus bridges, address decoders, and state-machine controllers in digital systems.
Key features of the EPM9320RI208-20 include four dedicated low-skew global input pins (typically used for clocks, clear, and output-enable distribution), a maximum internal operating frequency of 100 MHz, in-system programmability via JTAG, and industrial-grade temperature operation. The 5.0-V VCCIO core supply makes it directly compatible with TTL/CMOS logic families popular in legacy industrial designs.
The MAX 9000 architecture employs an enhanced EEPROM process and a fast interconnect matrix to deliver predictable timing across all 320 macro cells. Each Logic Array Block (LAB) contains 16 macro cells feeding the Programmable Interconnect Array (PIA), and the device includes 52 I/O pins in the 208-pin RQFP footprint with multiple I/O standards supported.
Typical applications include industrial automation controllers, glue-logic integration in microprocessor designs, bus-interface bridging, address decoding, and state-machine implementation in telecommunications and embedded systems. The non-volatile EEPROM configuration cell ensures instant-on behavior with no external boot PROM required.
When designing with this device, ensure that VCC rises monotonically during power-up and that the JTAG pins (TDI, TMS, TCK, TDO) are correctly terminated to support in-system programming. The four dedicated input pins provide low-skew clock distribution across the entire device and should be preferred for global timing signals.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, enabling faster sourcing decisions for legacy 5-V MAX 9000 designs.
直接替换替代料： EPM9320RI208-20 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9320RI208-20 （相同外形与封装尺寸） ——差异在于 Package, In-System Programmability, Operating Temperature, RoHS Status, Usable Gates.
快速对比工具——选择替代料号进行并排对比：
EPM9320RI208-10N
✅ 直接替换✓ 有现货
$27.2 / 个
查看数据手册 →EPM9320RI208-15
✅ 直接替换📋 参考替代料（不在目录中）
EPM9320RC208-20
✅ 直接替换✓ 有现货
$21.9 / 个
查看数据手册 →EPM9320RC208-20N
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9320RC208-15N
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9320RC208-15
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9320RC208-10
✅ 直接替换✓ 有现货
$26.4 / 个
查看数据手册 →EPM9320RI208-20 最大额定值与电气特性
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage (VCC) | 5.0 V |
| Logic Elements / LABs | 20 Logic Array Blocks (16 macro cells each) |
| Programmable Interconnect | Programmable Interconnect Array (PIA) |
| In-System Programmability | Yes - IEEE 1149.1 JTAG, 5.0-V ISP |
| Dedicated Input Pins | 4 (low-skew global) |
| 封装 | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature Grade | Industrial |
| Technology | CMOS EEPROM |
| 安装类型 | Surface Mount |
EPM9320RI208-20 引脚配置
| 引脚 1 | I/O — User I/O pin (signal direction programmable) |
| 引脚 2 | I/O — User I/O pin |
| 引脚 3 | I/O — User I/O pin |
| 引脚 4 | GCLK1 — Dedicated global clock input 1 (low-skew) |
| 引脚 5 | I/O — User I/O pin |
| 引脚 6 | I/O — User I/O pin |
| 引脚 7 | OE1 — Dedicated global output enable input 1 |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | I/O — User I/O pin |
| 引脚 10 | I/O — User I/O pin |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — User I/O pin |
| 引脚 13 | I/O — User I/O pin |
| 引脚 14 | I/O — User I/O pin |
| 引脚 15 | CLR1 — Dedicated global clear input 1 |
| 引脚 16 | I/O — User I/O pin |
| 引脚 17 | I/O — User I/O pin |
| 引脚 18 | VCC — 5.0-V supply voltage |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | I/O — User I/O pin |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | GCLK2 — Dedicated global clock input 2 (low-skew) |
| 引脚 23 | I/O — User I/O pin |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | OE2 — Dedicated global output enable input 2 |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | I/O — User I/O pin |
| 引脚 28 | I/O — User I/O pin |
| 引脚 29 | I/O — User I/O pin |
| 引脚 30 | GND — Ground |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | TDI — JTAG Test Data In |
| 引脚 34 | I/O — User I/O pin |
| 引脚 35 | TMS — JTAG Test Mode Select |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | TCK — JTAG Test Clock |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | VCC — 5.0-V supply voltage |
| 引脚 41 | TDO — JTAG Test Data Out |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | I/O — User I/O pin |
| 引脚 44 | I/O — User I/O pin |
| 引脚 45 | CLR2 — Dedicated global clear input 2 |
| 引脚 46 | I/O — User I/O pin |
| 引脚 47 | I/O — User I/O pin |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | I/O — User I/O pin |
| 引脚 51 | GND — Ground |
| 引脚 52 | I/O — User I/O pin |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | I/O — User I/O pin |
| 引脚 56 | I/O — User I/O pin |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | VCC — 5.0-V supply voltage |
| 引脚 59 | I/O — User I/O pin |
| 引脚 60 | I/O — User I/O pin |
| 引脚 61 | I/O — User I/O pin |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | GND — Ground |
| 引脚 66 | I/O — User I/O pin |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | I/O — User I/O pin |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | VCC — 5.0-V supply voltage |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | I/O — User I/O pin |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | I/O — User I/O pin |
| 引脚 78 | I/O — User I/O pin |
| 引脚 79 | GND — Ground |
| 引脚 80 | I/O — User I/O pin |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | I/O — User I/O pin |
| 引脚 84 | I/O — User I/O pin |
| 引脚 85 | I/O — User I/O pin |
| 引脚 86 | VCC — 5.0-V supply voltage |
| 引脚 87 | I/O — User I/O pin |
| 引脚 88 | I/O — User I/O pin |
| 引脚 89 | I/O — User I/O pin |
| 引脚 90 | I/O — User I/O pin |
| 引脚 91 | I/O — User I/O pin |
| 引脚 92 | I/O — User I/O pin |
| 引脚 93 | GND — Ground |
| 引脚 94 | I/O — User I/O pin |
| 引脚 95 | I/O — User I/O pin |
| 引脚 96 | I/O — User I/O pin |
| 引脚 97 | I/O — User I/O pin |
| 引脚 98 | I/O — User I/O pin |
| 引脚 99 | I/O — User I/O pin |
| 引脚 100 | VCC — 5.0-V supply voltage |
| 引脚 101 | I/O — User I/O pin |
| 引脚 102 | I/O — User I/O pin |
| 引脚 103 | I/O — User I/O pin |
| 引脚 104 | I/O — User I/O pin |
| 引脚 105 | I/O — User I/O pin |
| 引脚 106 | I/O — User I/O pin |
| 引脚 107 | GND — Ground |
| 引脚 108 | I/O — User I/O pin |
| 引脚 109 | I/O — User I/O pin |
| 引脚 110 | I/O — User I/O pin |
| 引脚 111 | I/O — User I/O pin |
| 引脚 112 | I/O — User I/O pin |
| 引脚 113 | I/O — User I/O pin |
| 引脚 114 | VCC — 5.0-V supply voltage |
| 引脚 115 | I/O — User I/O pin |
| 引脚 116 | I/O — User I/O pin |
| 引脚 117 | I/O — User I/O pin |
| 引脚 118 | I/O — User I/O pin |
| 引脚 119 | I/O — User I/O pin |
| 引脚 120 | I/O — User I/O pin |
| 引脚 121 | GND — Ground |
| 引脚 122 | I/O — User I/O pin |
| 引脚 123 | I/O — User I/O pin |
| 引脚 124 | I/O — User I/O pin |
| 引脚 125 | I/O — User I/O pin |
| 引脚 126 | I/O — User I/O pin |
| 引脚 127 | I/O — User I/O pin |
| 引脚 128 | VCC — 5.0-V supply voltage |
| 引脚 129 | I/O — User I/O pin |
| 引脚 130 | I/O — User I/O pin |
| 引脚 131 | I/O — User I/O pin |
| 引脚 132 | I/O — User I/O pin |
| 引脚 133 | I/O — User I/O pin |
| 引脚 134 | I/O — User I/O pin |
| 引脚 135 | GND — Ground |
| 引脚 136 | I/O — User I/O pin |
| 引脚 137 | I/O — User I/O pin |
| 引脚 138 | I/O — User I/O pin |
| 引脚 139 | I/O — User I/O pin |
| 引脚 140 | I/O — User I/O pin |
| 引脚 141 | I/O — User I/O pin |
| 引脚 142 | VCC — 5.0-V supply voltage |
| 引脚 143 | I/O — User I/O pin |
| 引脚 144 | I/O — User I/O pin |
| 引脚 145 | I/O — User I/O pin |
| 引脚 146 | I/O — User I/O pin |
| 引脚 147 | I/O — User I/O pin |
| 引脚 148 | I/O — User I/O pin |
| 引脚 149 | GND — Ground |
| 引脚 150 | I/O — User I/O pin |
| 引脚 151 | I/O — User I/O pin |
| 引脚 152 | I/O — User I/O pin |
| 引脚 153 | I/O — User I/O pin |
| 引脚 154 | I/O — User I/O pin |
| 引脚 155 | I/O — User I/O pin |
| 引脚 156 | VCC — 5.0-V supply voltage |
| 引脚 157 | I/O — User I/O pin |
| 引脚 158 | I/O — User I/O pin |
| 引脚 159 | I/O — User I/O pin |
| 引脚 160 | I/O — User I/O pin |
| 引脚 161 | I/O — User I/O pin |
| 引脚 162 | I/O — User I/O pin |
| 引脚 163 | GND — Ground |
| 引脚 164 | I/O — User I/O pin |
| 引脚 165 | I/O — User I/O pin |
| 引脚 166 | I/O — User I/O pin |
| 引脚 167 | I/O — User I/O pin |
| 引脚 168 | I/O — User I/O pin |
| 引脚 169 | I/O — User I/O pin |
| 引脚 170 | VCC — 5.0-V supply voltage |
| 引脚 171 | I/O — User I/O pin |
| 引脚 172 | I/O — User I/O pin |
| 引脚 173 | I/O — User I/O pin |
| 引脚 174 | I/O — User I/O pin |
| 引脚 175 | I/O — User I/O pin |
| 引脚 176 | I/O — User I/O pin |
| 引脚 177 | GND — Ground |
| 引脚 178 | I/O — User I/O pin |
| 引脚 179 | I/O — User I/O pin |
| 引脚 180 | I/O — User I/O pin |
| 引脚 181 | I/O — User I/O pin |
| 引脚 182 | I/O — User I/O pin |
| 引脚 183 | I/O — User I/O pin |
| 引脚 184 | VCC — 5.0-V supply voltage |
| 引脚 185 | I/O — User I/O pin |
| 引脚 186 | I/O — User I/O pin |
| 引脚 187 | I/O — User I/O pin |
| 引脚 188 | I/O — User I/O pin |
| 引脚 189 | I/O — User I/O pin |
| 引脚 190 | I/O — User I/O pin |
| 引脚 191 | GND — Ground |
| 引脚 192 | I/O — User I/O pin |
| 引脚 193 | I/O — User I/O pin |
| 引脚 194 | I/O — User I/O pin |
| 引脚 195 | I/O — User I/O pin |
| 引脚 196 | I/O — User I/O pin |
| 引脚 197 | I/O — User I/O pin |
| 引脚 198 | VCC — 5.0-V supply voltage |
| 引脚 199 | I/O — User I/O pin |
| 引脚 200 | I/O — User I/O pin |
| 引脚 201 | I/O — User I/O pin |
| 引脚 202 | I/O — User I/O pin |
| 引脚 203 | I/O — User I/O pin |
| 引脚 204 | I/O — User I/O pin |
| 引脚 205 | GND — Ground |
| 引脚 206 | I/O — User I/O pin |
| 引脚 207 | I/O — User I/O pin |
| 引脚 208 | I/O — User I/O pin |
典型应用
EPM9320RI208-20 适用于 6 应用s: Industrial Automation Controllers, Glue Logic and Address Decoding, Telecommunications Bus Bridges, State Machine Implementation, Embedded System Peripheral Expansion, Legacy System Modernization and Form-Fit Replacements.
Industrial Automation Controllers
The EPM9320RI208-20 is well-suited for industrial automation controllers because its 320 macro cells and 6,000 usable gates provide enough logic density for complex state machines, encoder/decoder logic, and PLC-style ladder replacement, while its industrial temperature grade and 5-V supply tolerance match factory-floor environments. The 100 MHz maximum operating frequency and 20 ns tPD allow deterministic timing for real-time control loops, and the EEPROM-based non-volatile configuration eliminates boot-time delays critical to machine startup. The 4 dedicated low-skew global input pins can distribute high-speed encoder signals across the chip without timing skew. Designers can implement glue logic between microcontrollers, sensor front-ends, and motor drivers on a single device.
推荐
Glue Logic and Address Decoding
The EPM9320RI208-20 excels as a glue-logic integration device for microprocessor systems where address decoding, chip-select generation, and wait-state insertion must be deterministic and instantly available at power-up. Its 320 macro cells and Programmable Interconnect Array (PIA) provide predictable timing regardless of routing, while the EEPROM configuration guarantees instant-on behavior without an external boot PROM. The 5-V VCC and TTL-compatible I/O allow direct connection to legacy 80C186, 68k, and 8051-family microprocessors without level translation. The device's 20 ns tPD comfortably decodes memory cycles in systems running up to 25 MHz, and the 208-pin RQFP package provides ample I/O for 16- and 32-bit bus implementations.
推荐
Telecommunications Bus Bridges
The EPM9320RI208-20 is frequently deployed in telecommunications equipment as a bus-bridge between legacy and modern interfaces, because its 320 macro cells and 6,000 usable gates can implement protocol converters (e.g., PCI-to-ISA, UART multiplexing, HDLC framing) on a single chip. The 5.0-V supply and TTL-compatible I/O simplify integration into legacy telecom linecards, while the IEEE 1149.1 JTAG interface allows in-field firmware updates as standards evolve. The 100 MHz maximum internal frequency supports common telecom clock domains, and the device's deterministic 20 ns tPD is ideal for synchronous bus turnaround. Industrial temperature operation is critical for outdoor or uncontrolled-environment installations.
推荐
State Machine Implementation
The EPM9320RI208-20 is ideally suited for complex state-machine controllers in embedded systems because its MAX 9000 macrocell architecture is designed around D-flip-flops with programmable output enables, making it straightforward to implement Moore and Mealy machines with 50+ states. The 20 LABs each provide 16 macro cells with shared local feedback, allowing efficient one-hot and binary state encoding without wasting logic. The deterministic 20 ns tPD and 100 MHz internal frequency ensure that even worst-case state transitions complete within budget. EEPROM configuration makes the device instantly ready at power-on, critical for safety interlocks and machine-tool controllers.
推荐
Embedded System Peripheral Expansion
The EPM9320RI208-20 is often used to expand the I/O capabilities of microcontrollers and embedded processors that lack sufficient native GPIO or peripheral interfaces. Its 208-pin RQFP package exposes a large number of user I/O pins that can be configured individually as input, output, or bidirectional, with TTL/CMOS-compatible thresholds directly matching 5-V microcontrollers. The 320 macro cells can implement PWM generators, quadrature decoders, SPI/I2C master/slave controllers, and UART channels on a single chip. The deterministic timing allows accurate PWM generation for motor control, and the JTAG ISP allows firmware updates without dismantling the end product.
推荐
Legacy System Modernization and Form-Fit Replacements
The EPM9320RI208-20 is widely used in legacy system modernization, particularly for industrial controls, medical devices, and aerospace systems built in the 1990s and 2000s, where the original Altera MAX 9000 design must be reproduced on a one-for-one basis. Its identical 208-pin RQFP footprint, JTAG-based ISP, and EEPROM configuration ensure that existing PCBs and design files can be supported without modification. Engineers can also migrate firmware from -20 speed grade to -15 or -10 speed grades without PCB changes, gaining timing margin while preserving the proven design. Industrial temperature grade and 5-V tolerance match the supply environment of legacy equipment.
推荐
推荐产品汇总
工程参考数据： EPM9320RI208-20 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9320RI208-10N | EPM9320RI208-15 | EPM9320RC208-20 | EPM9320RC208-20N | EPM9320RC208-15N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Propagation Delay (tPD) | 20 ns | 10 ns | 15 ns | 20 ns | 20 ns | 15 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | Industrial | Industrial | Industrial | Commercial | Commercial | Commercial |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Lead-Free (N suffix) | No | Yes (N suffix) | No | No | Yes (N suffix) | Yes (N suffix) |
关键差异点
- Industry-standard 5-V CPLD with EEPROM non-volatile configuration （对比 EPM9320RI208-10N)
- Industrial temperature grade vs commercial grade （对比 EPM9320RC208-20)
- Largest MAX 9000 device in 208-pin RQFP （对比 EPM7256SQC208-10)
设计说明
The EPM9320RI208-20 operates from a single 5.0-V VCC supply and the datasheet requires that VCC rise monotonically during power-up to ensure proper EEPROM configuration load. Place decoupling capacitors (0.1 uF ceramic in parallel with 10 uF tantalum or low-ESR electrolytic) as close as possible to every VCC pin on the package to minimize supply noise. There are typically 11 VCC and 11 GND pins distributed around the 208-pin RQFP perimeter for optimal power distribution. Estimated: typical VCCIO current consumption for the EPM9320 family is 100-300 mA depending on toggle rate and output loading, so the regulator should be sized with at least 30% headroom.
The 208-pin RQFP package requires careful PCB layout because of its high pin count (0.5 mm pitch) and gull-wing leads. Use 4-layer PCB stack-up with continuous power and ground planes; route signal traces on inner layers for controlled impedance where needed. The four dedicated global input pins (GCLK1, GCLK2, OE1/OE2, CLR1/CLR2) should be routed with matched trace lengths to minimize clock skew across the device. Estimated: the exposed thermal pad is not present on RQFP packages, so thermal management relies on copper pour around the perimeter.
JTAG boundary-scan integrity is essential for in-system programming of the EPM9320RI208-20. Ensure TDI, TMS, TCK, and TDO traces are kept short and free of stubs; add 10 kohm pull-ups on TDI, TMS, and TCK to prevent floating state during power-up. The minimum DC input voltage on user I/O pins is -0.5 V (and -0.3 V on dedicated inputs) - inputs may undershoot to -2.0 V for periods shorter than 20 ns under no-load conditions, but this must not be exceeded. Place series termination resistors on long JTAG chains to suppress ringing.
A common pitfall when designing with the EPM9320RI208-20 is assuming sufficient macro cells remain after synthesis - the design must fit within 320 macro cells and the available PIA routing. Always run a Quartus or MAX+PLUS II fitter report to confirm 100% utilization is achievable; pin-to-pin tPD of 20 ns only holds when the design is fully routed. The -20 speed grade is the slowest in the MAX 9320 family; do not use it for designs requiring >25 MHz register-to-register timing. Use the EPM9320RI208-10 (10 ns tPD) instead for high-frequency state machines or high-speed bus bridges.
合规信息
Lead-free status depends on -N suffix variant. The base EPM9320RI208-20 is non-N (with lead). RoHS and REACH compliance not explicitly stated in the verified web data - mark as unknown per data authenticity rules.