EPM9320RC208-20N vs EPM9320RI208-20N 对比
详细并排对比 EPM9320RC208-20N 出自 Altera 和 EPM9320RI208-20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320RC208-20N | EPM9320RI208-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $0.00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9320) |
| Logic Type | Complex Programmable Logic Device (CPLD) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 6,000 | — |
| Macro Cells | 320 | — |
| Logic Array Blocks | 20 | — |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| 电源电压 | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, 5.0 V ISP via JTAG |
| User I/O Pins | 168 | — |
| 封装 | 208-pin RQFP (PowerQuad II) | 208-pin PQFP (Plastic Quad Flat Pack) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Macrocells | — | 320 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| 工作温度范围 | — | -40C to +85C (Industrial) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |