EPM9320RI208-10N vs EPM9320ARI208-10N 对比

详细并排对比 EPM9320RI208-10N 出自 Altera 和 EPM9320ARI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N ✓ 量产中

规格对比

参数 EPM9320RI208-10N EPM9320ARI208-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $27.20 $16.20
Family MAX 9000 MAX 9000
Device Type Complex Programmable Logic Device (CPLD) —
Usable Gates 6,000 6,000
Macro Cells 320 —
Logic Array Blocks (LABs) 20 20
Pin-to-Pin Propagation Delay (tPD) 10 ns —
Maximum System Clock Frequency 100 MHz —
电源电压 5 V 4.5 V to 5.5 V
I/O Voltage 5 V —
User I/O Pins 160 —
封装 208-pin RQFP (PowerQuad II) 208-pin RQFP (S-PQFP-G208)
安装类型 Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes (JTAG/ISP) —
工作温度范围 -40C to +85C (industrial) —
RoHS 状态 Compliant (N suffix = lead-free) unknown
Lead Finish Lead-free (matte tin) —
MSL 等级 [DATA_NEEDED: MSL level] —
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 320
Maximum Operating Frequency — 144.9 MHz
Propagation Delay (tPD) — 10 ns (speed grade -10)
工作温度 — -40 C to +85 C (industrial)
Process Technology — CMOS EEPROM
Programmability — In-system (ISP) via IEEE 1149.1 JTAG
Global Dedicated Inputs — 16
Architecture — Multiple Array MatriX (MAX) third-generation

数据手册与资源

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