EPM9320RI208-10N vs EPM9320ARI208-10N Comparison

Detailed side-by-side comparison of EPM9320RI208-10N by Altera and EPM9320ARI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N βœ“ Active

Specification Comparison

Parameter EPM9320RI208-10N EPM9320ARI208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.20 $16.20
Family MAX 9000 MAX 9000
Device Type Complex Programmable Logic Device (CPLD) β€”
Usable Gates 6,000 6,000
Macro Cells 320 β€”
Logic Array Blocks (LABs) 20 20
Pin-to-Pin Propagation Delay (tPD) 10 ns β€”
Maximum System Clock Frequency 100 MHz β€”
Supply Voltage 5 V 4.5 V to 5.5 V
I/O Voltage 5 V β€”
User I/O Pins 160 β€”
Package 208-pin RQFP (PowerQuad II) 208-pin RQFP (S-PQFP-G208)
Mounting Type Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) β€”
In-System Programmability Yes (JTAG/ISP) β€”
Operating Temperature Range -40C to +85C (industrial) β€”
RoHS Status Compliant (N suffix = lead-free) unknown
Lead Finish Lead-free (matte tin) β€”
MSL Level [DATA_NEEDED: MSL level] β€”
Product Type β€” CPLD (Complex Programmable Logic Device)
Macrocells β€” 320
Maximum Operating Frequency β€” 144.9 MHz
Propagation Delay (tPD) β€” 10 ns (speed grade -10)
Operating Temperature β€” -40 C to +85 C (industrial)
Process Technology β€” CMOS EEPROM
Programmability β€” In-system (ISP) via IEEE 1149.1 JTAG
Global Dedicated Inputs β€” 16
Architecture β€” Multiple Array MatriX (MAX) third-generation

Datasheets & Resources

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