EPM9320RI208-20N vs EPM9320RI208-10N 对比
详细并排对比 EPM9320RI208-20N 出自 Altera 和 EPM9320RI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320RI208-20N | EPM9320RI208-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $27.20 |
| Device Family | MAX 9000 (EPM9320) | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 320 | — |
| Flip-Flops | 484 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V or 5 V configurable | — |
| 封装 | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| Package Lead Pitch | 0.500 mm | — |
| Number of Terminals | 208 | — |
| 工作温度范围 | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| In-System Programmability | Yes, 5.0 V ISP via JTAG | Yes (JTAG/ISP) |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Dedicated Input Pins | 4 (low-skew global distribution) | — |
| Minimum DC Input on I/O Pins | -0.5 V | — |
| Minimum DC Input on Dedicated Inputs | -0.3 V | — |
| Input Undershoot/ Overshoot | -2.0 V / 7.0 V for <20 ns (no-load) | — |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Family | — | MAX 9000 |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Usable Gates | — | 6,000 |
| Macro Cells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| 电源电压 | — | 5 V |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Lead Finish | — | Lead-free (matte tin) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |