EPM9320RI208-20N vs EPM9320RI208-10N Comparaison
Comparaison détaillée côte à côte de EPM9320RI208-20N par Altera et EPM9320RI208-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9320RI208-20N | EPM9320RI208-10N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $27,20 |
| Device Family | MAX 9000 (EPM9320) | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 320 | — |
| Flip-Flops | 484 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V or 5 V configurable | — |
| Boîtier | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| Package Lead Pitch | 0.500 mm | — |
| Number of Terminals | 208 | — |
| Plage de température de fonctionnement | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| In-System Programmability | Yes, 5.0 V ISP via JTAG | Yes (JTAG/ISP) |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Dedicated Input Pins | 4 (low-skew global distribution) | — |
| Minimum DC Input on I/O Pins | -0.5 V | — |
| Minimum DC Input on Dedicated Inputs | -0.3 V | — |
| Input Undershoot/ Overshoot | -2.0 V / 7.0 V for <20 ns (no-load) | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Family | — | MAX 9000 |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Usable Gates | — | 6,000 |
| Macro Cells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| Tension d'alimentation | — | 5 V |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Lead Finish | — | Lead-free (matte tin) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |