EPM9560ARC240-10 vs EPM9560ARC208-10 对比

详细并排对比 EPM9560ARC240-10 出自 Altera 和 EPM9560ARC208-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARC240-10 EPM9560ARC208-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $28.80 $0.00
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX) - third generation —
Usable Gates 12,000 12,000 gates
Macrocells 560 560 macrocells
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz 144.9 MHz
Propagation Delay (tpd) 11.4 ns —
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM —
封装 240-pin PowerQuad QFP (RQFP / EAR240) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
工作温度 0C to +70C (commercial) 0 C to +70 C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) —
Logic Family CMOS CMOS
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000A (Multiple Array MatriX)
Programmable Logic Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks — 35 LABs
User I/O Pins — 153 I/O
Propagation Delay (tPD) — 10 ns (speed grade -10)
电源电压 — 5.0 V
Configuration Technology — EEPROM (non-volatile, in-system programmable)
JTAG Interface — IEEE 1149.1 boundary-scan (ISP)
安装类型 — Surface Mount
引脚数量 — 208 pins

数据手册与资源

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