EPM9560GC280-20 vs EPM9560GC280-15N 对比

详细并排对比 EPM9560GC280-20 出自 Altera 和 EPM9560GC280-15N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560GC280-20 EPM9560GC280-15N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $360.00 $125.00
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 12,000 12,000 (typical)
Macrocells 560 —
Maximum User I/O 212 —
Pin-to-Pin Delay 20 ns (speed grade -20) —
Counter Frequency (max) 100 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) —
I/O Voltage 3.3 V or 5.0 V configurable —
Process Technology CMOS EEPROM —
封装 280-pin CPGA (Ceramic Pin Grid Array) CPGA-280 (Ceramic Pin Grid Array, 280 pins)
工作温度 [DATA_NEEDED: commercial/industrial/military grade] —
In-System Programming Yes, via IEEE 1149.1 JTAG —
安装类型 Through-Hole (CPGA socket) —
RoHS 状态 [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] —
Device Family — MAX 9000
Product Type — EE PLD / CPLD
Macrocell Count — 560
Propagation Delay (tPD) — 16.6 ns
最大时钟频率 — 117.6 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Maximum Supply Voltage — 5.25 V
Logic Technology — CMOS EEPROM
In-System Programmability — Yes (5.0-V ISP via JTAG)
Boundary-Scan (JTAG) — IEEE Std. 1149.1 compliant
Package Code — PGA / CPGA280
Terminal Form — PIN/PEG
Operating Temperature Grade — Commercial
Architecture — Multiple Array MatriX (MAX) 3rd generation

数据手册与资源

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