EPM9560GC280-20 vs EPM9560GC280-15N Comparison
Detailed side-by-side comparison of EPM9560GC280-20 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560GC280-20 | EPM9560GC280-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 (typical) |
| Macrocells | 560 | — |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | — |
| Package | 280-pin CPGA (Ceramic Pin Grid Array) | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | — |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| Mounting Type | Through-Hole (CPGA socket) | — |
| RoHS Status | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | — |
| Device Family | — | MAX 9000 |
| Product Type | — | EE PLD / CPLD |
| Macrocell Count | — | 560 |
| Propagation Delay (tPD) | — | 16.6 ns |
| Maximum Clock Frequency | — | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Maximum Supply Voltage | — | 5.25 V |
| Logic Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| Boundary-Scan (JTAG) | — | IEEE Std. 1149.1 compliant |
| Package Code | — | PGA / CPGA280 |
| Terminal Form | — | PIN/PEG |
| Operating Temperature Grade | — | Commercial |
| Architecture | — | Multiple Array MatriX (MAX) 3rd generation |