EPM9560GC280-20N vs EPM9560GC280-15N 对比

详细并排对比 EPM9560GC280-20N 出自 Altera 和 EPM9560GC280-15N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560GC280-20N EPM9560GC280-15N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $285.00 $125.00
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX), 3rd generation Multiple Array MatriX (MAX) 3rd generation
Technology CMOS EEPROM-based —
Usable Gates 6,000 to 12,000 12,000 (typical)
Macrocells 560 —
User I/O Pins 212 —
Pin-to-Pin Delay (tPD) 20 ns —
Maximum Counter Frequency 144 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
I/O Voltage 3.3 V or 5 V (configurable) —
In-System Programmability Yes (5.0-V ISP via IEEE 1149.1 JTAG) Yes (5.0-V ISP via JTAG)
封装 280-pin CPGA (Ceramic Pin Grid Array) CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Configuration Memory EEPROM (non-volatile, instant-on) —
PCI Compliance Yes —
工作温度 [DATA_NEEDED: industrial/commercial grade] —
RoHS 状态 [DATA_NEEDED] —
Device Family — MAX 9000
Product Type — EE PLD / CPLD
Macrocell Count — 560
Propagation Delay (tPD) — 16.6 ns
最大时钟频率 — 117.6 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Maximum Supply Voltage — 5.25 V
Logic Technology — CMOS EEPROM
Boundary-Scan (JTAG) — IEEE Std. 1149.1 compliant
Package Code — PGA / CPGA280
Terminal Form — PIN/PEG
Operating Temperature Grade — Commercial

数据手册与资源

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