EPM9560RC210-20 vs EPM9560RC208-21 对比
详细并排对比 EPM9560RC210-20 出自 Altera 和 EPM9560RC208-21 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
EPM9560RC208-21 ⚠ 最后一次采购规格对比
| 参数 | EPM9560RC210-20 | EPM9560RC208-21 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $60.00 | $22.95 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| 封装 | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Clock-to-Output (tCO) | 12 ns | — |
| Maximum User I/O | [DATA_NEEDED: 212 I/O per datasheet, package-dependent] | 149 |
| 电源电压 | 5 V | 5.0 V |
| Process Technology | 0.65 um EEPROM | — |
| In-System Programmability | Yes (MAX+PLUS II flow) | Yes (IEEE Std. 1149.1 JTAG) |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| 工作温度 | [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] | [DATA_NEEDED: industrial or commercial grade -21 suffix] |
| 安装类型 | Surface Mount | — |
| RoHS 状态 | RoHS3 Compliant (per supplier listing) | [DATA_NEEDED: confirm RoHS compliance for -21 variant] |
| Architecture | — | Multiple Array MatriX (MAX), third-generation |
| Technology | — | CMOS EEPROM-based |
| Flip-Flops | — | 772 |
| Propagation Delay (speed grade -21) | — | 21 ns (max, per speed grade designation) |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (per variant) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Security Bit | — | Yes (programmable) |