EPM9560RC240-15W vs EPM9560RC240-15N 对比

详细并排对比 EPM9560RC240-15W 出自 Altera 和 EPM9560RC240-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-15W EPM9560RC240-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.00 $27.85
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Device Type Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 12,000
Macrocells 560 560
User I/O Pins 191 —
Pin-to-Pin Delay 15 ns —
Internal Frequency 117.6 MHz —
电源电压 4.75 V to 5.25 V 5.0 V
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes (ISP via JTAG) —
封装 240-pin RQFP (PowerQuad) with exposed pad RQFP-240 (240-pin Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) 0C to +70C (Commercial)
Logic Family CMOS CMOS (EEPROM-based)
引脚数 240 —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
MSL 等级 [DATA_NEEDED: MSL level] —
Series — MAX 9000
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

数据手册与资源

浏览全部产品 创建 BOM 获取报价