EPM9560RC240-15W vs EPM9560RC240-15N Comparison

Detailed side-by-side comparison of EPM9560RC240-15W by Altera and EPM9560RC240-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC240-15W EPM9560RC240-15N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Device Type Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 12,000
Macrocells 560 560
User I/O Pins 191 —
Pin-to-Pin Delay 15 ns —
Internal Frequency 117.6 MHz —
Supply Voltage 4.75 V to 5.25 V 5.0 V
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes (ISP via JTAG) —
Package 240-pin RQFP (PowerQuad) with exposed pad RQFP-240 (240-pin Plastic Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0C to +70C (Commercial)
Logic Family CMOS CMOS (EEPROM-based)
Number of Pins 240 —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
MSL Level [DATA_NEEDED: MSL level] —
Series — MAX 9000
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

Datasheets & Resources

Browse All Products Create BOM Request Quote