EPM9560RC240-2 vs EPM9560RC240-15N 对比

详细并排对比 EPM9560RC240-2 出自 Altera 和 EPM9560RC240-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-2 EPM9560RC240-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $180.00 $27.85
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Logic Elements 560 macrocells —
Usable Gates 12,000 12,000
Pin-to-Pin Delay 2 ns (speed grade -2) —
Maximum Frequency 100 MHz —
电源电压 5 V 5.0 V
User I/O Count 212 —
封装 240-pin RQFP (Metric QFP) RQFP-240 (240-pin Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1), in-system programmable —
Non-Volatile Configuration Yes (EEPROM-based) —
工作温度 [DATA_NEEDED: commercial/industrial grade] 0C to +70C (Commercial)
RoHS 状态 Non-compliant (5V RQFP, pre-RoHS era) [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Lead-Free No (legacy Sn/Pb process) —
Logic Block Count [DATA_NEEDED: LAB count] —
Series — MAX 9000
Macrocells — 560
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

数据手册与资源

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