EPM9560RC240-2 vs EPM9560RC240-15N Comparison
Detailed side-by-side comparison of EPM9560RC240-2 by Altera and EPM9560RC240-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC240-2 | EPM9560RC240-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 (third-generation Multiple Array MatriX) |
| Logic Elements | 560 macrocells | — |
| Usable Gates | 12,000 | 12,000 |
| Pin-to-Pin Delay | 2 ns (speed grade -2) | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage | 5 V | 5.0 V |
| User I/O Count | 212 | — |
| Package | 240-pin RQFP (Metric QFP) | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | — |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| Operating Temperature | [DATA_NEEDED: commercial/industrial grade] | 0C to +70C (Commercial) |
| RoHS Status | Non-compliant (5V RQFP, pre-RoHS era) | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Lead-Free | No (legacy Sn/Pb process) | — |
| Logic Block Count | [DATA_NEEDED: LAB count] | — |
| Series | — | MAX 9000 |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Internal Counter Frequency (fCNT) | — | 145 MHz |
| Global Setup Time (tFSU) | — | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | — | [DATA_NEEDED: tFCO for -15 grade] |
| Logic Family | — | CMOS (EEPROM-based) |
| Programmability | — | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |