EPM9560RC240-20N vs EPM9560RC240-15N 对比

详细并排对比 EPM9560RC240-20N 出自 Altera 和 EPM9560RC240-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-20N EPM9560RC240-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.00 $27.85
Device Family MAX 9000 (EPM9560) —
Logic Type Complex Programmable Logic Device (CPLD) —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 35 35
Maximum User I/O Pins 216 216
Pin-to-Pin Propagation Delay (tPD1) 20 ns —
Internal Counter Frequency (fCNT) 144 MHz 145 MHz
Flip-Flop Setup Time (tSU) 3.0 ns —
电源电压 5.0 V 5.0 V
Configuration Technology EEPROM (in-system programmable) —
封装 240-pin RQFP (PowerQuad Flat Pack) RQFP-240 (240-pin Plastic Quad Flat Pack)
工作温度 0 C to +70 C (commercial) 0C to +70C (Commercial)
安装类型 Surface Mount Surface Mount
Speed Grade -20 (20 ns) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Lead-Free Status [DATA_NEEDED: lead-free status] —
Series — MAX 9000
Family — MAX 9000 (third-generation Multiple Array MatriX)
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

数据手册与资源

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