EPM9560RCRC304-15 vs EPM9560RC304-15 对比
详细并排对比 EPM9560RCRC304-15 出自 Altera 和 EPM9560RC304-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560RCRC304-15 | EPM9560RC304-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $9.40 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | — |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 117.6 MHz | — |
| 电源电压 | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | On-chip EEPROM (non-volatile) |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | — |
| 封装 | 304-pin RQFP (PowerQuad Flat Pack) | 304-pin RQFP (Plastic Quad Flat Pack) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度范围 | [DATA_NEEDED: operating temperature range] | — |
| Number of User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX), EEPROM-based |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: lead-free / RoHS compliance status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Macrocells | — | 560 |
| User I/O Pins | — | 212 (maximum) |
| Propagation Delay (tPD) | — | 15 ns (combinatorial, pin-to-pin) |
| 引脚数量 | — | 304 |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Standard | — | 5.0 V TTL / PCI-compliant |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Technology Node | — | High-performance CMOS, EEPROM process |
| 工作温度 | — | [DATA_NEEDED: industrial/commercial temperature grade] |