EPM9560RCRC304-15 vs EPM9560RC304-15 비교
다음의 상세 나란히 비교: EPM9560RCRC304-15 제조: Altera 및 EPM9560RC304-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9560RCRC304-15 | EPM9560RC304-15 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $0.00 | $9.40 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | — |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 117.6 MHz | — |
| 공급 전압 | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | On-chip EEPROM (non-volatile) |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | — |
| 패키지 | 304-pin RQFP (PowerQuad Flat Pack) | 304-pin RQFP (Plastic Quad Flat Pack) |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 범위 | [DATA_NEEDED: operating temperature range] | — |
| Number of User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX), EEPROM-based |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: lead-free / RoHS compliance status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Macrocells | — | 560 |
| User I/O Pins | — | 212 (maximum) |
| Propagation Delay (tPD) | — | 15 ns (combinatorial, pin-to-pin) |
| 핀 수 | — | 304 |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Standard | — | 5.0 V TTL / PCI-compliant |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Technology Node | — | High-performance CMOS, EEPROM process |
| 동작 온도 | — | [DATA_NEEDED: industrial/commercial temperature grade] |