EPM9560RI208-15N vs EPM9320RI208-20N 对比

详细并排对比 EPM9560RI208-15N 出自 Altera 和 EPM9320RI208-20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI208-15N EPM9320RI208-20N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $19.45 $0.00
Manufacturer Altera (Intel Programmable Solutions Group) —
Device Family MAX 9000 MAX 9000 (EPM9320)
Device Type EPLD (Erasable Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX), 3rd generation —
Configuration Memory CMOS EEPROM, in-system programmable EEPROM (non-volatile)
封装 208-pin RQFP (Ruggedized Quad Flat Pack) 208-pin PQFP (Plastic Quad Flat Pack)
Total Pins 356 (per third-party catalog; see _validation_note) —
Package Pin Count 208 —
Terminal Form Gull Wing —
Package Code HFQFP —
User I/Os 216 (per DigiChip specification; see _validation_note) —
Maximum Internal Frequency 145 MHz —
Propagation Delay (tPD) 11.4 ns (15 ns speed grade) 20 ns
Speed Grade -15 —
电源电压 5.0 V —
工作温度 0C to 70C (Commercial) —
Temperature Grade Industrial (per Vyrian/Partstack listings) —
Logic Family CMOS —
Programming Interface IEEE 1149.1 JTAG, 5.0-V in-system —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells — 320
Flip-Flops — 484
Supply Voltage (VCC) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5 V configurable
Package Lead Pitch — 0.500 mm
Number of Terminals — 208
工作温度范围 — -40C to +85C (Industrial)
In-System Programmability — Yes, 5.0 V ISP via JTAG
JTAG Interface — IEEE Std. 1149.1 compliant
Dedicated Input Pins — 4 (low-skew global distribution)
Minimum DC Input on I/O Pins — -0.5 V
Minimum DC Input on Dedicated Inputs — -0.3 V
Input Undershoot/ Overshoot — -2.0 V / 7.0 V for <20 ns (no-load)
安装类型 — Surface Mount

数据手册与资源

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