EPM9560RI208-15N vs EPM9320RI208-20N Comparison
Detailed side-by-side comparison of EPM9560RI208-15N by Altera and EPM9320RI208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-15N | EPM9320RI208-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Device Family | MAX 9000 | MAX 9000 (EPM9320) |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | — |
| Configuration Memory | CMOS EEPROM, in-system programmable | EEPROM (non-volatile) |
| Package | 208-pin RQFP (Ruggedized Quad Flat Pack) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | — |
| Package Pin Count | 208 | — |
| Terminal Form | Gull Wing | — |
| Package Code | HFQFP | — |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | — |
| Maximum Internal Frequency | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | 20 ns |
| Speed Grade | -15 | — |
| Supply Voltage | 5.0 V | — |
| Operating Temperature | 0C to 70C (Commercial) | — |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 320 |
| Flip-Flops | — | 484 |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| Operating Temperature Range | — | -40C to +85C (Industrial) |
| In-System Programmability | — | Yes, 5.0 V ISP via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |
| Mounting Type | — | Surface Mount |