EPM9560RI208-20 vs EPM9560R1208-20 对比

详细并排对比 EPM9560RI208-20 出自 Intel 和 EPM9560R1208-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI208-20 EPM9560R1208-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $21.10 $22.40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Usable Gates 12,000 6,000
Macro Cells 560 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 —
Pin-to-Pin Propagation Delay (tPD) 20 ns —
Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 5.0 V —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes (IEEE 1149.1 JTAG)
封装 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm R-1208 (BGA-style fine-pitch)
工作温度 [DATA_NEEDED: operating temperature range grade] 0C to +70C (commercial)
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: confirm via current distributor data]
安装类型 Surface Mount Surface Mount
Macrocells — 560
Logic Array Blocks — 52 (typical for 560 macrocells)
Maximum User I/O — 212
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

数据手册与资源

浏览全部产品 创建 BOM 获取报价