EPM9560RI240-15N vs EPM9560RI240-15 对比

详细并排对比 EPM9560RI240-15N 出自 Intel 和 EPM9560RI240-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI240-15N EPM9560RI240-15
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $23.10
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Logic Family MAX 9000 (Multiple Array MatriX) —
Macrocells 560 560
Flip-Flops 772 772
Usable Gates 12,000 —
User I/O Pins 216 —
封装 240-pin RQFP (PowerQuad Flat Pack) RQFP-240 (Power Quad Flat Pack, gull-wing, 0.500 mm pitch)
Pin-to-Pin Propagation Delay 15 ns —
Internal Frequency 145 MHz —
电源电压 5.0 V —
I/O Voltage Compatibility 3.3 V or 5.0 V configurable —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE 1149.1 (JTAG) boundary scan —
工作温度范围 -40 C to +85 C (industrial) —
安装类型 Surface Mount Surface Mount
RoHS 状态 RoHS3 Compliant —
Moisture Sensitivity Level MSL 3 (168 hours) —
Manufacturer Standard Lead Time 1-7 days (distributor stock) —
Product Type — EE PLD (Electrically Erasable Programmable Logic Device)
Family — MAX 9000
User I/Os (industrial grade) — 191
Dedicated Inputs — 4
Propagation Delay (tPD) — 15 ns (speed grade -15)
Internal Frequency (max) — 145 MHz
Logic Family / Process — CMOS, EEPROM-based
Core Voltage — 5.0 V
I/O Voltage — 3.3 V or 5.0 V (configurable)
Architecture — Multiple Array MatriX (MAX), 3rd generation
工作温度 — -40 C to +85 C (industrial)
In-System Programmability — Yes, JTAG (IEEE Std 1149.1)
Power-Up Configuration — Instant-on (no external boot PROM)
I/O Undershoot Tolerance — -2.0 V for <20 ns (no-load)
I/O Overshoot Tolerance — 7.0 V for <20 ns (no-load)

数据手册与资源

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