MPC7410VS500LE vs MPC7410VS400LE 对比
详细并排对比 MPC7410VS500LE 出自 NXP Semiconductors 和 MPC7410VS400LE 出自 NXP Semiconductors。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
NXP Semiconductors
MPC7410VS500LE - PowerPC G4 MPU, 500MHz, 360-FCCLGA | NXP
MPC7410VS500LE ⚠ 最后一次采购规格对比
| 参数 | MPC7410VS500LE | MPC7410VS400LE |
|---|---|---|
| 品牌 | NXP Semiconductors | NXP Semiconductors |
| 分类 | Microcontrollers | Microcontrollers |
| 生命周期状态 | 最后采购期 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $162.00 | $21.00 |
| Manufacturer | NXP USA Inc. (formerly Freescale, originally Motorola) | NXP Semiconductors (formerly Freescale) |
| Product Type | 32-bit Embedded Microprocessor (MPU) | — |
| Series | MPC74xx (NITRO) | MPC74xx PowerPC G4 |
| Core | PowerPC G4, 1 Core | — |
| Architecture | Power Architecture with AltiVec SIMD | — |
| 数据总线宽度 | 32-bit | 32-bit (64-bit external per parametric records) |
| 最大时钟频率 | 500 MHz | 400 MHz |
| Silicon Revision | R1.4 | — |
| 工作温度 | 0 °C to 105 °C (NITRO industrial) | -40C to +105C (industrial "LE" grade per Mouser listing) |
| Process Technology | 0.13 µm CMOS | 0.18 um CMOS |
| Core / I/O Voltage | 1.8 V core / 2.5 V I/O (typical) | — |
| L1 Cache | 32 KB instruction + 32 KB data | — |
| SIMD Engine | AltiVec 128-bit vector unit | — |
| FPU | Hardware double-precision floating-point | — |
| MMU | Yes (BookE-enhanced PowerPC) | — |
| System Bus | MPX high-bandwidth bus | — |
| 封装 | 360-FCCLGA, 25 x 25 mm, flip-chip ceramic BGA | — |
| Lead-Free (Pb-Free) | Yes (LE suffix) | — |
| RoHS 状态 | Compliant | [DATA_NEEDED: lead-free / RoHS confirmation per datasheet label] |
| 安装类型 | Surface Mount | Surface Mount (LGA socket or solder) |
| Core Architecture | — | PowerPC G4 RISC |
| Core Count | — | 1 |
| 电源电压 | — | 1.8 V / 2.5 V / 3.3 V |
| 封装 / 外壳 | — | 360-FCCLGA (Flip-Chip Ceramic LGA), 25 x 25 mm |
| Pin / Ball Count | — | 360 |
| Tray Packaging | — | Tray (per FindIC parametric record) |
| Lead-Free / PB-Free | — | Yes (per Mouser description: "PB FREE") |
| Instruction Set | — | PowerPC RISC |
| On-Chip Cache | — | L1 (instruction + data); L2 (per family datasheet) |