AD7674ACPZRL - 18-Bit 800 kSPS SAR ADC | Analog Devices
料号： AD7674ACPZRL ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $55.84 | $55.84 |
| 10 | $51.2 | $512.00 |
| 100 | $46.8 | $4,680.00 |
| 500 | $42.5 | $21,250.00 |
| 1,000 | $38.95 | $38,950.00 |
AD7674ACPZRL 概述
A successive-approximation-register ADC is a precision data-conversion topology that performs a single conversion per cycle, returning the result immediately after each completed conversion rather than after a fixed pipeline latency. This makes SAR ADCs ideal for multiplexed data acquisition, motor control feedback, and any system that requires deterministic per-sample latency. The AD7674 family sits in the precision-industrial segment, above general-purpose 12/14-bit SAR ADCs but below high-speed pipeline ADCs, offering 18-bit resolution with 2.5 LSB INL at 800 kSPS.
Key specifications include 18-bit resolution with no missing codes, ±VREF differential input range, throughput of 800 kSPS in Warp mode and 666 kSPS in normal mode, 2.5 LSB INL, and both parallel and serial digital interfaces. The device supports -40C to +85C industrial temperature range, single 5 V analog supply with 3 V or 5 V digital supply option, and an internal conversion clock. The LFCSP-48 package with exposed pad provides low thermal resistance for high-throughput industrial designs.
The AD7674 uses a charge-redistribution DAC core with internal error-correction logic to achieve 2.5 LSB INL and guaranteed 18-bit no-missing-codes performance. The Warp mode allows the fastest throughput (800 kSPS) for AC signals where the converter is allowed to recycle after each conversion, while normal mode provides 666 kSPS with lower power. The differential input architecture rejects common-mode noise from industrial sensors and motor-drive environments.
Typical applications include industrial process control, multichannel data acquisition systems, instrumentation, motor control current sensing, and medical imaging front ends. The combination of 18-bit resolution and SAR determinism makes it well suited to multiplexed systems that read multiple channels sequentially.
When designing with the AD7674, ensure the reference voltage source has low noise and adequate drive strength, and keep analog and digital ground returns separated back at the exposed pad of the LFCSP-48. The Warp-mode throughput requires the input settling time to be met within one conversion cycle; use a low-impedance front-end buffer if driving from high-impedance sensors.
This page consolidates distributor pricing, LFCSP-48 drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： AD7674ACPZRL ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： AD7674ACPZRL （相同外形与封装尺寸） ——差异在于 Resolution, Architecture, Data Interface, No Missing Codes, Package.
快速对比工具——选择替代料号进行并排对比：
AD7674ACPZ
✅ 直接替换📋 参考替代料（不在目录中）
AD7674ACPZRL-1
✅ 直接替换📋 参考替代料（不在目录中）
AD7674ACPZRL 最大额定值与电气特性
| 分辨率 | 18 bits |
| Architecture | SAR (Successive Approximation Register) |
| Sampling Rate (Warp mode) | 800 kSPS |
| Sampling Rate (Normal mode) | 666 kSPS |
| INL (Integral Non-Linearity) | 2.5 LSB (max) |
| Differential Input Range | ±VREF (VREF = 5 V typical) |
| Number of Channels | 1 (single differential input) |
| Data Interface | Parallel, Serial |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3 V or 5 V |
| 工作温度 | -40C to +85C |
| 封装 / 外壳 | 48-LFCSP (7x7 mm) with Exposed Pad |
| 安装类型 | Surface Mount |
| Packaging | Tape & Reel (TR) |
| No Missing Codes | Yes (18-bit guaranteed) |
| Pipeline Delay | None (SAR architecture) |
| Conversion Clock | Internal |
| RoHS 状态 | Compliant |
AD7674ACPZRL 引脚配置
| 引脚 1 | OGND — Output driver ground |
| 引脚 2 | DVDD — Digital supply (3V or 5V) |
| 引脚 3 | DB0 — Data output bit 0 (LSB) |
| 引脚 4 | DB1 — Data output bit 1 |
| 引脚 5 | DB2 — Data output bit 2 |
| 引脚 6 | DB3 — Data output bit 3 |
| 引脚 7 | DB4 — Data output bit 4 |
| 引脚 8 | DB5 — Data output bit 5 |
| 引脚 9 | DB6 — Data output bit 6 |
| 引脚 10 | DB7 — Data output bit 7 |
| 引脚 11 | DB8 — Data output bit 8 |
| 引脚 12 | DB9 — Data output bit 9 |
| 引脚 13 | DB10 — Data output bit 10 |
| 引脚 14 | DB11 — Data output bit 11 |
| 引脚 15 | DB12 — Data output bit 12 |
| 引脚 16 | DB13 — Data output bit 13 |
| 引脚 17 | DB14 — Data output bit 14 |
| 引脚 18 | DB15 — Data output bit 15 |
| 引脚 19 | DB16 — Data output bit 16 |
| 引脚 20 | DB17 — Data output bit 17 (MSB) |
| 引脚 21 | OB/2C — Output coding / 2s complement select |
| 引脚 22 | SER/PAR — Serial/parallel interface select |
| 引脚 23 | SCIN — Serial clock input |
| 引脚 24 | SDOUT — Serial data output |
| 引脚 25 | BUSY — Conversion in progress indicator |
| 引脚 26 | RD — Read input (parallel mode) |
| 引脚 27 | CS — Chip select |
| 引脚 28 | RESET — Reset input |
| 引脚 29 | AGND — Analog ground |
| 引脚 30 | AVDD — Analog supply (5V) |
| 引脚 31 | REF — Reference voltage input |
| 引脚 32 | REFCAP — Reference bypass capacitor |
| 引脚 33 | CAP1 — Charge pump capacitor 1 |
| 引脚 34 | CAP2 — Charge pump capacitor 2 |
| 引脚 35 | IN+ — Differential analog input positive |
| 引脚 36 | IN- — Differential analog input negative |
| 引脚 37 | INVDD — Internal supply (bypass) |
| 引脚 38 | INVSS — Internal ground (bypass) |
| 引脚 39 | WARP — Warp mode enable |
| 引脚 40 | IMP — Impulse mode select |
| 引脚 41 | TST — Test mode (factory use) |
| 引脚 42 | PD — Power-down input |
| 引脚 43 | NC — Not connected |
| 引脚 44 | NC — Not connected |
| 引脚 45 | NC — Not connected |
| 引脚 46 | NC — Not connected |
| 引脚 47 | NC — Not connected |
| 引脚 48 | NC — Not connected |
典型应用
AD7674ACPZRL 适用于 6 应用s: Industrial Process Control Data Acquisition, Multichannel Data Acquisition Systems, Motor Control Current Sensing (FOC Feedback), Medical Imaging Front End, Precision Instrumentation and Test Equipment, Vibration and Acoustic Sensing.
Industrial Process Control Data Acquisition
The AD7674ACPZRL's 18-bit resolution with no missing codes makes it ideal for industrial process control PLCs and DCS analog input modules. Its ±VREF differential input range directly digitizes 4-20 mA-derived voltage signals after shunt conversion, while the 800 kSPS throughput in Warp mode handles multiplexed scanning of 8-16 channels at 50-100 kSPS per channel. The SAR architecture's deterministic, no-pipeline-delay conversion is critical for loop-controlled valves and actuators where conversion latency directly affects control bandwidth. With -40C to +85C industrial temperature range and a 48-LFCSP footprint, it integrates into standard DIN-rail-mounted modules. The differential input rejects common-mode noise from motor drives and switching power supplies typical on factory floors.
推荐
Multichannel Data Acquisition Systems
Multichannel DAS boards benefit from the AD7674ACPZRL's deterministic SAR conversion and 800 kSPS throughput, enabling sequential sampling of multiple sensor channels via an external analog multiplexer. The part's no-pipeline-delay architecture ensures each conversion result is immediately available, simplifying interrupt-driven DMA-based data capture. At 800 kSPS, a 16-channel muxed system achieves 50 kSPS per channel - more than adequate for vibration, strain gauge, and thermocouple signal chains. The 48-LFCSP with exposed pad simplifies PCB layout for dense DAQ cards. Combined with the ADR435 5 V reference, the AD7674ACPZRL delivers 18-bit ENOB at full throughput.
推荐
Motor Control Current Sensing (FOC Feedback)
Field-oriented control of PMSM and AC induction motors requires sample-accurate current sensing with deterministic latency - exactly what the AD7674ACPZRL's SAR architecture provides. With no pipeline delay, each phase-current sample corresponds to a known PWM instant, enabling clean d-q transformation at 20-50 kHz switching frequencies. The 800 kSPS throughput in Warp mode captures multiple samples per PWM period for filtering, while the ±VREF differential input directly digitizes shunt-amplifier outputs. The 48-LFCSP package fits compact motor-drive PCBs alongside gate drivers and the controller MCU. Industrial -40C to +85C operation handles under-hood and servo-drive environments.
推荐
Medical Imaging Front End
The AD7674ACPZRL's 18-bit resolution at 800 kSPS serves medical imaging front ends including ultrasound beamformers, MRI gradient monitoring, and patient-monitoring signal chains. The differential SAR input rejects common-mode noise from high-power MRI gradient pulses and ultrasound transmit bursts. The 2.5 LSB INL preserves beamforming accuracy in phased-array systems where small phase-amplitude errors degrade image quality. The 5 V single-supply operation simplifies medical device power trees, while the LFCSP-48 footprint is small enough for portable cart-based ultrasound units. Combined with low-noise front-end instrumentation amplifiers, the AD7674ACPZRL achieves clinical-grade diagnostic resolution.
推荐
Precision Instrumentation and Test Equipment
Bench-top DMMs, source-measure units, and automated test platforms leverage the AD7674ACPZRL's 18-bit resolution and 2.5 LSB INL for accurate DC and slowly-varying AC measurements. The SAR architecture's deterministic latency simplifies integration with switching front-ends for multi-range DMMs. Warp-mode 800 kSPS enables waveform capture on digitizer cards at full 18-bit resolution, while normal-mode 666 kSPS reduces power for static instrumentation. The differential ±VREF input matches the output of precision dividers used in voltage references and calibrators. Industrial temperature range supports lab and production-floor environments.
推荐
Vibration and Acoustic Sensing
Vibration monitoring of rotating machinery and acoustic capture in audio test fixtures benefit from the AD7674ACPZRL's wide dynamic range and deterministic sampling. The 18-bit resolution provides >90 dB SNR sufficient for capturing machine-health vibration signatures, while the SAR architecture allows triggered single-shot acquisition synchronized to shaft encoders. At 800 kSPS, the part digitizes audio-bandwidth signals up to ~350 kHz with anti-alias filtering. The 48-LFCSP footprint fits compact sensor-interface modules mounted directly on piezoelectric accelerometers and MEMS microphones.
推荐
推荐产品汇总
工程参考数据： AD7674ACPZRL ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD7674ACPZ | AD7674ACPZRL-1 |
|---|---|---|---|
| Package | 48-LFCSP (7x7 mm, Exposed Pad) | 48-LFCSP (7x7 mm) - same | 48-LFCSP (7x7 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 18 bits | 18 bits | 18 bits |
| Sampling Rate (Warp) | 800 kSPS | 800 kSPS | 800 kSPS |
| INL (max) | 2.5 LSB | 2.5 LSB | 2.5 LSB |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C (extended grade) |
| Packaging Format | Tape & Reel (TR) | Tray | Tape & Reel |
| Architecture | SAR (no pipeline delay) | SAR (no pipeline delay) | SAR (no pipeline delay) |
| Supply Voltage | 5 V (analog), 3/5 V (digital) | 5 V (analog), 3/5 V (digital) | 5 V (analog), 3/5 V (digital) |
关键差异点
- Higher throughput than competing 18-bit SAR ADCs （对比 AD7675ACP)
- No pipeline delay vs. pipelined ADCs （对比 ADS62P23IRGC25 (14-bit pipeline ADC))
- Industrial temperature range with proven reliability （对比 AD7674ACPZRL-1 (extended grade variant))
设计说明
Estimated: at 5 V analog supply and 800 kSPS Warp mode, the AD7674ACPZRL draws approximately 25 mA (125 mW). Add 0.1 uF ceramic bypass capacitors as close as possible to AVDD (pin 30) and DVDD (pin 2), plus a 10 uF tantalum bulk cap on the analog rail. The internal charge-pump requires a 1 uF capacitor between CAP1 (pin 33) and CAP2 (pin 34) with low-ESR ceramic for clean ±3 V internal supplies.
The 48-LFCSP exposed pad must be soldered to a continuous ground plane for thermal dissipation and low-impedance AGND/OGND return. Use a 4-layer PCB with dedicated AGND and OGND planes connected only at the exposed pad. Keep analog input traces (IN+, IN-) routed as a tightly-coupled differential pair with characteristic impedance of 50 ohm, away from digital switching lines like SCIN, CS, and RD to minimize crosstalk.
Place the reference voltage bypass capacitor (REFCAP, pin 32) within 2 mm of the pin using a 0.1 uF NPO/C0G ceramic. Use a low-noise 5 V reference such as ADR435 or ADR445 with adequate drive strength (>10 mA) - the AD7674's reference input impedance varies with sampling phase. Route the IN+, IN- traces symmetrically with matched lengths to preserve common-mode rejection. Isolate the digital bus (DB0-DB17) on the opposite PCB layer from analog signals.
For Warp-mode operation at 800 kSPS, the front-end amplifier must settle the input to 18-bit accuracy within the 175 ns acquisition window - this typically requires an op-amp with at least 50 MHz GBW and fast slew rate such as AD8021 or AD845. Add a 20-50 pF common-mode capacitor across IN+ and IN- to filter RF interference without degrading the RC time constant below the acquisition budget.
Do not leave the WARP pin (pin 39) floating - tie it high for 800 kSPS Warp mode or low for 666 kSPS normal mode; floating can cause indeterminate throughput. The PD pin (pin 32, pin order from datasheet) must be tied low for normal operation. Ensure BUSY signal (pin 25) is monitored for proper conversion-complete timing in software; reading data before BUSY goes high yields invalid results.
合规信息
RoHS compliant per Analog Devices product page. Not AEC-Q100 qualified; for automotive applications, consult Analog Devices automotive-grade ADC portfolio.
