AD7679ASTZRL - 18-Bit 570 kSPS SAR ADC | Analog Devices
料号： AD7679ASTZRL ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.75 | $267.50 |
| 100 | $23.95 | $2,395.00 |
| 500 | $21.5 | $10,750.00 |
| 1,000 | $19.2 | $19,200.00 |
AD7679ASTZRL 概述
A SAR ADC is a type of data converter that performs a binary-search conversion on a held analog input, returning one bit per clock cycle with no latency. SAR ADCs sit within the broader data-acquisition hierarchy of data converters -> ADCs -> successive-approximation ADCs -> high-precision instrumentation ADCs, and are valued for their deterministic latency, excellent DC linearity, and zero pipeline-delay behavior compared to pipeline or delta-sigma architectures.
Key features include 2.5 LSB maximum INL (no missing codes), 100 dB typical SNR at 2 kHz input (VREF = 5 V), on-chip reference buffer, and single 5 V supply operation. Power dissipation is 76 mW at 500 kSPS and scales down to 150 µW at 1 kSPS for low-duty-cycle acquisition. The AD7679 is a pin-to-pin compatible upgrade of the AD7674, AD7676, and AD7678, allowing direct performance upgrades on existing 48-LQFP boards.
The part uses Analog Devices' PulSAR architecture with an internal conversion clock, internal reference buffer, and selectable serial or parallel interface. The 5 V/3 V interface is compatible with SPI, QSPI, MICROWIRE, and DSP hosts. The 48-LQFP variant supports both serial and parallel modes, while the 48-LFCSP variant is intended for space-constrained serial-mode designs.
Typical applications include industrial process control loops, multichannel data-acquisition boards, medical instrumentation front ends, spectrum and vibration analysis, and any 18-bit precision measurement channel where deterministic SAR latency simplifies system-level synchronization.
When designing, ensure the input driver amplifier settles to better than 18-bit accuracy within the acquisition window. The AD8021 is the typical choice; verify settling at 18-bit level rather than 0.1% because 18-bit settling is far more demanding. Decouple AVDD and DVDD separately and place the reference bypass capacitor close to the REF pin.
This page synthesizes distributor pricing, pin-compatible alternatives within the PulSAR family, and PCB-level design notes not found in the standalone manufacturer datasheet.
直接替换替代料： AD7679ASTZRL ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： AD7679ASTZRL （相同外形与封装尺寸） ——差异在于 Architecture, No Missing Codes, Package, Pipeline Delay, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
AD7679ASTZ
✅ 直接替换📋 参考替代料（不在目录中）
AD7679ACPZRL
✅ 直接替换✓ 有现货
$24.1 / 个
查看数据手册 →AD7674ACPZRL
✅ 直接替换✓ 有现货
$38.95 / 个
查看数据手册 →AD7678ASTZ
✅ 直接替换📋 参考替代料（不在目录中）
AD7676ASTZ
✅ 直接替换📋 参考替代料（不在目录中）
ADS8482IBRGZR
✅ 直接替换✓ 有现货
$14.45 / 个
查看数据手册 →AD7679ASTZRL 最大额定值与电气特性
| 分辨率 | 18 bits |
| Architecture | SAR (PulSAR) |
| 采样率 | 570 kSPS |
| Input Channels | 1 differential |
| Input Range | ±VREF (VREF = 5 V typical) |
| INL (Max) | ±2.5 LSB (no missing codes) |
| SNR | 100 dB typ at 2 kHz (VREF = 5 V) |
| Data Interface | Serial (SPI/QSPI/MICROWIRE/DSP) and Parallel (18-/16-/8-bit) |
| Pipeline Delay | None (SAR) |
| 电源电压 | 5 V single supply |
| Power Dissipation | 76 mW at 500 kSPS; 150 µW at 1 kSPS |
| 封装 | 48-pin LQFP (7x7 mm) |
| 安装类型 | Surface Mount |
| 工作温度 | -40C to +85C |
| RoHS 状态 | Compliant |
| Pin-to-Pin Compatible | AD7674, AD7676, AD7678 |
AD7679ASTZRL 引脚配置
| 引脚 1 | DVDD — Digital 5 V supply |
| 引脚 2 | DGND — Digital ground |
| 引脚 3 | AVDD — Analog 5 V supply |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | REF — 5 V reference input/output, decouple to AGND |
| 引脚 6 | REFGND — Reference ground |
| 引脚 7 | IN+ — Differential analog input positive |
| 引脚 8 | IN- — Differential analog input negative |
| 引脚 9 | AGND — Analog ground |
| 引脚 10 | AVDD — Analog 5 V supply |
| 引脚 11 | NC — Not connected (per datasheet) |
| 引脚 12 | NC — Not connected (per datasheet) |
| 引脚 13 | OB/2C — Output bus / 2's complement select |
| 引脚 14 | IMP — Input mode select |
| 引脚 15 | WARP — Warp/Impulse mode select |
| 引脚 16 | SER/PAR — Serial/Parallel interface select |
| 引脚 17 | EXT/INT — Internal/External clock select |
| 引脚 18 | INVSCLK — Invert SCLK select |
| 引脚 19 | INVCLK — Invert CLK select |
| 引脚 20 | RD — Read input (parallel mode) |
| 引脚 21 | CNVST — Conversion start input |
| 引脚 22 | BUSY — Busy output (low during conversion) |
| 引脚 23 | DGND — Digital ground |
| 引脚 24 | DVDD — Digital 5 V supply |
| 引脚 25 | DB0 — Parallel data bit 0 / serial LSB |
| 引脚 26 | DB1 — Parallel data bit 1 |
| 引脚 27 | DB2 — Parallel data bit 2 |
| 引脚 28 | DB3 — Parallel data bit 3 |
| 引脚 29 | DB4 — Parallel data bit 4 |
| 引脚 30 | DB5 — Parallel data bit 5 |
| 引脚 31 | DB6 — Parallel data bit 6 |
| 引脚 32 | DB7 — Parallel data bit 7 |
| 引脚 33 | DB8 — Parallel data bit 8 |
| 引脚 34 | DB9 — Parallel data bit 9 |
| 引脚 35 | DB10 — Parallel data bit 10 |
| 引脚 36 | DB11 — Parallel data bit 11 |
| 引脚 37 | DB12 — Parallel data bit 12 |
| 引脚 38 | DB13 — Parallel data bit 13 |
| 引脚 39 | DB14 — Parallel data bit 14 |
| 引脚 40 | DB15 — Parallel data bit 15 |
| 引脚 41 | DB16 — Parallel data bit 16 |
| 引脚 42 | DB17 — Parallel data bit 17 / serial MSB |
| 引脚 43 | SCLK — Serial clock (serial mode) |
| 引脚 44 | SDOUT — Serial data output |
| 引脚 45 | DGND — Digital ground |
| 引脚 46 | DVDD — Digital 5 V supply |
| 引脚 47 | AVDD — Analog 5 V supply |
| 引脚 48 | AGND — Analog ground (exposed pad) |
典型应用
AD7679ASTZRL 适用于 6 应用s: Industrial Process Control Loops, Multichannel Data Acquisition Systems, Medical Instrumentation Front Ends, Vibration and Spectrum Analysis, Precision Weigh Scales and Force Measurement, Audio Test and Measurement.
Industrial Process Control Loops
The AD7679ASTZRL fits industrial process-control front ends because its 570 kSPS throughput handles multiple multiplexed 4-20 mA or voltage channels, while ±2.5 LSB INL with no missing codes preserves loop calibration accuracy. Placed at the ADC stage of a PLC or DCS analog input card, paired with an AD8021 driver for input settling, the part's deterministic SAR latency simplifies synchronization with the host DSP. The single 5 V supply and 48-LQFP footprint ease integration into standard industrial card form factors, and -40C to +85C operation tolerates factory-floor enclosures.
推荐
Multichannel Data Acquisition Systems
The AD7679ASTZRL is well matched to multichannel data-acquisition boards where the zero pipeline delay of the SAR architecture simplifies channel-to-channel timing. With 570 kSPS throughput, eight channels can be sampled at roughly 70 kSPS each, while the parallel 18-bit bus mode enables fast DMA-style transfers to an FPGA. The 48-LQFP footprint allows a compact analog island with separate AVDD/DVDD routing. Power dissipation scales linearly with throughput, dropping to 150 µW at 1 kSPS for duty-cycled monitoring.
推荐
Medical Instrumentation Front Ends
The AD7679ASTZRL's 100 dB SNR at 2 kHz and 18-bit no-missing-codes performance suits patient-monitoring front ends such as ECG, SpO2, and infusion-pump feedback loops. The differential ±VREF input range naturally accommodates biopotential signals centered around mid-supply, and the SAR architecture's deterministic latency simplifies medical-device software certification. Power dissipation of 76 mW at 500 kSPS is acceptable for line-powered instruments; for battery-powered patient wearables the 150 µW at 1 kSPS mode is attractive.
推荐
Vibration and Spectrum Analysis
The AD7679ASTZRL is appropriate for vibration and dynamic-signal acquisition because its 570 kSPS rate covers the harmonics needed for accelerometer and acoustic-vibration analysis up to the Nyquist band. SAR architecture provides single-cycle conversions with no group delay, so FFT windows align cleanly with mechanical events. The 100 dB SNR floor accommodates dynamic-range requirements of structural-health monitoring and modal-analysis systems. Multiple AD7679 channels can be synchronized via the CNVST and BUSY pins for cross-axis measurements.
推荐
Precision Weigh Scales and Force Measurement
The AD7679ASTZRL fits digital weigh-scale and load-cell designs where 18-bit resolution and 2.5 LSB INL are required to resolve microgram-level mass changes after the load-cell excitation is ratiometric. The differential input accepts the load-cell bridge output directly when VREF is tied to the excitation rail. Zero pipeline delay ensures each force reading is a true snapshot at the conversion instant, important for high-speed in-motion checkweighers. The 48-LQFP package drops onto standard scale-meter controller PCBs.
推荐
Audio Test and Measurement
The AD7679ASTZRL is useful in audio-bandwidth test and measurement, where 570 kSPS sampling comfortably exceeds the 192 kSPS required for 96 kHz audio, and 18-bit resolution captures dynamic range above CD quality. Audio analyzer front ends can route line-level inputs through a programmable-gain stage, then into the differential ADC input. The SAR architecture's deterministic latency suits loopback measurements where group delay must be characterized. The 48-LQFP footprint fits bench-instrument card cages alongside DSP and DAC companions.
推荐
推荐产品汇总
工程参考数据： AD7679ASTZRL ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD7679ASTZ | AD7679ACPZRL | AD7674ACPZRL | AD7678ASTZ | ADS8482IBRGZR |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Texas Instruments |
| Package | 48-LQFP (7x7) | 48-LQFP (7x7) - same | 48-LQFP family (verify LFCSP/LQFP code) | 48-LQFP family (verify LFCSP/LQFP code) | 48-LQFP (7x7) - same | 48-LQFP (verify footprint) |
| Resolution | 18 bits | 18 bits | 18 bits | 16 bits | 18 bits | |
| Sample Rate | 570 kSPS | 570 kSPS | 800 kSPS (+40%) | 500 kSPS (-12%) | 1 MSPS (+75%) | |
| Architecture | SAR | SAR | SAR | SAR | SAR | |
| Supply | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single | |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
关键差异点
- Pin-to-pin upgrade path within the PulSAR family （对比 AD7674ACPZRL / AD7676ASTZ / AD7678ASTZ)
- Zero pipeline delay for deterministic timing （对比 Pipeline ADCs in the 18-bit class)
- Differential ±VREF input range with on-chip reference buffer （对比 Single-ended, low-voltage ADCs in the same throughput class)
设计说明
Verified: AD8021 is the recommended input driver per the Analog Devices AD7679 datasheet. The driver MUST settle to better than 18-bit accuracy (≈ 4 ppm, ≈ 20 µV at 5 V full-scale) within the acquisition window. Settling specified at 0.1% or 0.01% in the op-amp data sheet is NOT sufficient for 18-bit accuracy; request 18-bit settling curves from the driver manufacturer or measure directly on the bench before committing to a layout. Under-driven inputs degrade INL and SNR in production boards even when prototype measurements look acceptable.
Estimated: the 48-LQFP exposes a thermal pad that doubles as AGND, so AGND must be stitched with at least 8 vias to a dedicated analog ground island. Keep digital return currents (DB0-DB17, SCLK, BUSY) routed to the digital ground island, and join analog and digital grounds at a single point near the ADC's AGND pin to avoid ground loops that inject digital noise into the analog input. Place 10 µF + 0.1 µF decoupling on each AVDD and DVDD pin within 5 mm of the lead, plus a 10 µF + 0.1 µF pair on the REF pin. Star-route the 5 V analog supply away from the digital 5 V rail.
Estimated: power dissipation is 76 mW at 500 kSPS and falls to 150 µW at 1 kSPS, a >500x dynamic range that lets designers duty-cycle the ADC for battery-powered monitoring. To reach the 150 µW figure, the CNVST pin must be toggled at 1 kSPS and the parallel bus must not be enabled continuously. If the application requires continuous streaming, assume 76 mW as the design budget. A ferrite bead between AVDD and the 5 V rail, plus bulk capacitance near the supply entry, isolates the ADC from upstream switching-converter ripple that would otherwise couple into the analog input via the reference.
Keep the IN+ and IN+ traces as a length-matched differential pair routed away from digital buses and clock lines. Guard the input traces with ground pours on both sides and below. The REF pin traces should be short and surrounded by ground on the same layer to minimize noise injection into the reference buffer. For serial mode, route SDOUT away from SCLK crossing to avoid coupling, and add a 50 Ω series termination if the bus length exceeds 50 mm.
合规信息
RoHS and REACH compliant per Analog Devices product page. Not AEC-Q100 qualified; not designed for automotive under-the-hood applications. Industrial (-40C to +85C) operating range.
