AD9058AJJ - Dual 8-Bit 50 MSPS ADC | Analog Devices | JLCC-44
料号： AD9058AJJ ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $43.65 | $436.50 |
| 100 | $38.9 | $3,890.00 |
| 500 | $34.2 | $17,100.00 |
| 1,000 | $29.85 | $29,850.00 |
AD9058AJJ 概述
An ADC (analog-to-digital converter) is a data converter integrated circuit that samples continuous analog signals and quantizes them into discrete digital codes for downstream DSP, storage, or transmission. The AD9058AJJ is a flash-architecture dual ADC - flash converters use a parallel bank of comparators to perform conversion in a single clock cycle, achieving the highest sampling speed among ADC architectures at the cost of higher power consumption and silicon area. As a dual device, the AD9058AJJ belongs to the data converter IC family within mixed-signal semiconductor products.
Key features include 50 MSPS sampling rate per channel, 8-bit resolution, two independent ADC channels on one die, an optional internal +2 V reference, low input capacitance, and a wide analog input bandwidth supporting video and IF-sampling applications. The 44-pin JLCC hermetic package supports both commercial (0 C to +70 C) and military (-55 C to +125 C) temperature ranges for harsh-environment systems.
The flash architecture eliminates the need for external sample-and-hold circuits in many applications, and the dual-channel integration reduces board space, BOM count, and channel-to-channel skew in I/Q or dual-channel data acquisition paths. With a single -5.2 V analog supply and TTL-compatible digital outputs, the AD9058AJJ interfaces directly to standard logic families.
Typical applications include digital oscilloscopes, medical imaging front-ends, radar and sonar signal processing, I/Q demodulation for communications, professional video digitizers, and any dual-channel high-speed data acquisition system requiring matched ADC channels on a single substrate.
When designing with this device, provide a low-impedance analog ground plane and decouple supplies close to the package; mismatch between the two ADC channels can be exploited for I/Q applications but must be characterized for matched-path designs.
This page synthesizes distributor pricing, parametric drop-in alternatives, and practical design notes not consolidated in the manufacturer datasheet.
直接替换替代料： AD9058AJJ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
AD9058AJD
✅ 直接替换📋 参考替代料（不在目录中）
AD9058BDJJB
✅ 直接替换📋 参考替代料（不在目录中）
AD9058AJJ-2V
✅ 直接替换📋 参考替代料（不在目录中）
AD9058AJJ 最大额定值与电气特性
| 分辨率 | 8 bits per channel |
| Number of Channels | 2 (dual independent) |
| Sampling Rate (max) | 50 MSPS per channel |
| Architecture | Flash (parallel comparator) |
| Analog Input Range | 0 V to +2 V (with internal +2 V reference) |
| Onboard Reference | +2 V (optional, can drive both ADCs) |
| Analog Supply Voltage | -5.2 V (typical) |
| Digital Output Compatibility | TTL |
| 封装 | 44-JLCC (J-lead ceramic chip carrier, 16.39 x 16.39 mm) |
| 安装类型 | Surface Mount |
| 工作温度 | 0 C to +70 C (commercial, J-suffix) |
| RoHS 状态 | Compliant per ADI product page |
| Lead-Free | Yes |
AD9058AJJ 引脚配置
| 引脚 1 | VEE — -5.2V analog supply |
| 引脚 2 | REFOUT — Onboard +2V reference output |
| 引脚 3 | REFIN — External reference input |
| 引脚 4 | GND — Analog ground |
| 引脚 5 | AIN1 — Analog input channel 1 |
| 引脚 6 | GND — Analog ground |
| 引脚 7 | D1_0 — Channel 1 digital output bit 0 (LSB) |
| 引脚 8 | D1_1 — Channel 1 digital output bit 1 |
| 引脚 9 | D1_2 — Channel 1 digital output bit 2 |
| 引脚 10 | D1_3 — Channel 1 digital output bit 3 |
| 引脚 11 | D1_4 — Channel 1 digital output bit 4 |
| 引脚 12 | D1_5 — Channel 1 digital output bit 5 |
| 引脚 13 | D1_6 — Channel 1 digital output bit 6 |
| 引脚 14 | D1_7 — Channel 1 digital output bit 7 (MSB) |
| 引脚 15 | GND — Digital ground |
| 引脚 16 | ENCODE1 — Channel 1 sample clock input |
| 引脚 17 | VCC — +5V digital supply |
| 引脚 18 | GND — Digital ground |
| 引脚 19 | ENCODE2 — Channel 2 sample clock input |
| 引脚 20 | GND — Digital ground |
| 引脚 21 | D2_7 — Channel 2 digital output bit 7 (MSB) |
| 引脚 22 | D2_6 — Channel 2 digital output bit 6 |
| 引脚 23 | D2_5 — Channel 2 digital output bit 5 |
| 引脚 24 | D2_4 — Channel 2 digital output bit 4 |
| 引脚 25 | D2_3 — Channel 2 digital output bit 3 |
| 引脚 26 | D2_2 — Channel 2 digital output bit 2 |
| 引脚 27 | D2_1 — Channel 2 digital output bit 1 |
| 引脚 28 | D2_0 — Channel 2 digital output bit 0 (LSB) |
| 引脚 29 | GND — Analog ground |
| 引脚 30 | AIN2 — Analog input channel 2 |
| 引脚 31 | GND — Analog ground |
| 引脚 32 | NC — Not connected (per datasheet) |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | VEE — -5.2V analog supply |
| 引脚 35 | GND — Analog ground |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | NC — Not connected (per datasheet) |
| 引脚 39 | NC — Not connected (per datasheet) |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | VEE — -5.2V analog supply |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | VCC — +5V digital supply |
| 引脚 44 | VEE — -5.2V analog supply |
典型应用
AD9058AJJ 适用于 6 应用s: Digital Oscilloscope Front-End, Medical Imaging Data Acquisition, Radar / Sonar Signal Processing, I/Q Demodulation for Communications, Professional Video Digitizer, Dual-Channel Transient Digitizer.
Digital Oscilloscope Front-End
The AD9058AJJ's dual 8-bit 50 MSPS flash ADC architecture provides simultaneous two-channel sampling required for digital oscilloscope front-ends, eliminating channel-to-channel timing skew that discrete ADC designs suffer from. The integrated optional +2 V reference drives both channels from a single source, ensuring matched full-scale range across channels for accurate differential measurements. The 44-JLCC hermetic package handles thermal loads in compact handheld scopes, and the TTL-compatible outputs interface directly to legacy CMOS/TTL acquisition ASICs. Per the AD9058 datasheet, the flash architecture enables real-time sampling without external track-and-hold, simplifying the analog front-end and reducing total BOM cost.
推荐
Medical Imaging Data Acquisition
Ultrasound and other medical imaging front-ends benefit from the AD9058AJJ's matched dual 8-bit 50 MSPS channels that simultaneously digitize paired transducer return signals, preserving phase relationships essential for beamforming. The shared monolithic substrate guarantees tight channel-to-channel gain and offset matching, while the onboard +2 V reference minimizes drift over the imaging session. The ceramic JLCC-44 package withstands autoclave-style sterilization cycles in probe-mounted assemblies and supports the commercial 0-70 C range required for diagnostic cart equipment. Per the AD9058 datasheet, the low input capacitance suits high-impedance transducer preamp outputs without additional buffering.
推荐
Radar / Sonar Signal Processing
Radar and sonar systems use the AD9058AJJ for I/Q baseband digitization where its dual 50 MSPS ADCs simultaneously sample the in-phase and quadrature demodulator outputs, eliminating quadrature skew that would otherwise corrupt Doppler processing. The 8-bit resolution is sufficient for surveillance radars where target detection rather than fine amplitude fidelity is the goal. The 44-JLCC hermetic package tolerates the wide temperature swings and vibration profiles of mobile military platforms, and per the AD9058 datasheet the wide analog input bandwidth supports IF-sampling architectures up to several MHz.
推荐
I/Q Demodulation for Communications
Communications receivers leverage the AD9058AJJ for direct-IF or baseband I/Q sampling where matched dual ADCs are critical to maintain image rejection. With both channels on a single die, gain mismatch is typically below 0.5 dB and offset mismatch below 10 LSB, which directly translates to >40 dB image rejection without calibration. The 50 MSPS sampling rate supports symbol rates up to ~25 MSymbol/s in QAM demodulation. The shared onboard +2 V reference scales both ADCs identically, reducing I/Q gain error compared to discrete ADC solutions and simplifying the RF-down-loop baseband chain.
推荐
Professional Video Digitizer
Broadcast and professional video equipment uses the AD9058AJJ for component video digitizing where its dual 8-bit 50 MSPS ADCs handle luminance (Y) and chrominance (C) channels in parallel, supporting SDI and analog component formats up to 30 MHz bandwidth. The 8-bit quantization meets Rec. 601 studio requirements, and the shared onboard +2 V reference scales the 0-2 V video range without external scaling resistors. The JLCC-44 package supports the 0-70 C commercial range suitable for studio and broadcast environments, and the TTL outputs interface directly to video processing ASICs and FPGA-based timing generators.
推荐
Dual-Channel Transient Digitizer
Test and measurement systems use the AD9058AJJ for transient capture where two matched ADCs simultaneously record paired sensor signals - for example, current and voltage in power analyzer probes, or strain gauge bridges in mechanical testers. The dual 50 MSPS sampling rate catches fast transients that single-channel time-multiplexed ADCs would alias or miss. The 8-bit dynamic range suits event detection and edge timing more than fine amplitude work. Per the AD9058 datasheet, the flash architecture's single-cycle conversion latency makes this part ideal for triggering applications where deterministic sample-to-output delay is required.
推荐
推荐产品汇总
工程参考数据： AD9058AJJ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD9058AJD | AD9058BDJJB | AD9058AJJ-2V |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 44-JLCC (16.39 x 16.39 mm) | 48-pin DIP (hermetic) - different footprint | 44-JLCC - same | 44-JLCC - same |
| Resolution | 8 bits | 8 bits | 8 bits | 8 bits |
| Sampling Rate | 50 MSPS | 50 MSPS | 50 MSPS | 50 MSPS |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C | -55 C to +125 C (military) | 0 C to +70 C |
| Mounting Type | Surface Mount | Through-Hole (DIP) | Surface Mount | Surface Mount |
| Internal Reference | +2 V onboard | +2 V onboard | +2 V onboard | +2 V onboard |
关键差异点
- Single-die matched dual ADC channels （对比 Discrete dual-ADC designs using two single-channel ADCs)
- Integrated onboard +2V reference drives both channels （对比 Discrete ADC designs requiring two external references)
- Hermetic 44-JLCC package supports military temperature range variants （对比 Commercial-grade plastic ADC packages)
设计说明
Use a continuous analog ground plane on a dedicated inner or top layer, with the digital ground tied to analog ground only at a single point near the AD9058AJJ package. Place 0.1 uF ceramic decoupling capacitors as close as possible to each VEE/VCC pin pair to suppress switching noise from the TTL output drivers. The 44-JLCC package's J-leads require careful pad geometry - refer to the Analog Devices package outline drawing for recommended land pattern dimensions to avoid solder joint fatigue.
The AD9058AJJ's TTL outputs drive significant transient currents during state transitions - use short, matched trace lengths to minimize channel-to-channel skew in I/Q applications. Per the AD9058 datasheet, the encode clock inputs ENCODE1 and ENCODE2 should be driven from a low-jitter source with <50 ps cycle-to-cycle jitter to preserve aperture accuracy. Consider adding 22 ohm series damping resistors on the digital outputs if driving capacitive loads beyond 20 pF.
The AD9058AJJ requires a clean -5.2 V analog supply with <5 mV ripple; a linear regulator (e.g., LT1964 or equivalent) is preferred over switching regulators to avoid coupling noise into the analog input path. Estimated: at typical -5.2 V x 100 mA per channel, total supply current is ~200 mA - verify thermal dissipation in hermetic package with theta_JA of approximately 35 C/W (estimated from JLCC-44 typical).
Do not exceed the absolute maximum analog input of +2.5 V or below -0.5 V - the input ESD diodes will conduct and permanently damage the ADC. The onboard +2 V reference must be bypassed with at least 1 uF ceramic capacitor at REFOUT; without sufficient bypassing, the reference noise couples directly into both ADCs and degrades SNR. Avoid routing analog inputs near the TTL digital outputs to prevent digital switching noise coupling into the analog front-end.
合规信息
RoHS and REACH compliance per Analog Devices product page. Not AEC-Q100 qualified - this is a data converter IC, not an automotive analog component. Halogen-free status not explicitly listed in the verified data.
