AD9268 - Dual 16-Bit 125 MSPS ADC | Analog Devices
料号： AD9268 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $45.32 | $45.32 |
| 10 | $41.87 | $418.70 |
| 100 | $36.54 | $3,654.00 |
| 500 | $32.1 | $16,050.00 |
| 1,000 | $28.75 | $28,750.00 |
AD9268 概述
An analog-to-digital converter (ADC) is a critical building block in signal processing chains, converting continuous analog signals into discrete digital values for processing by DSPs, FPGAs, or microcontrollers. The AD9268 belongs to the family of high-speed, high-resolution ADCs, positioned between lower-speed precision converters and ultra-high-speed RF-sampling converters. Its dual-channel architecture enables simultaneous sampling of two signals, which is essential for I/Q demodulation in communications receivers and for multi-phase monitoring in industrial systems.
Key features of the AD9268 include a 16-bit resolution with a maximum sample rate of 125 MSPS, a spurious-free dynamic range (SFDR) of 90 dBc, and a signal-to-noise ratio (SNR) of 78 dBFS. The device supports both 1.8 V and 3.3 V digital output levels, and its power dissipation is typically 1.2 W at 125 MSPS. The AD9268 is pin-compatible with the AD9258 (14-bit), allowing a simple migration path between resolutions. It also shares pin compatibility with the AD9251, AD9231, and AD9204 families for lower sample rate, low-power applications.
Technically, the AD9268 uses a multi-stage pipelined architecture with digital error correction, achieving high linearity and low noise. The internal voltage reference can be overridden via the SENSE pin for external reference operation, providing flexibility in gain and full-scale range settings. The device includes a clock duty cycle stabilizer, which maintains performance even with non-50% duty cycle clocks, and a data output format selectable between offset binary and twos complement.
Typical applications include communications receivers (cellular base stations, point-to-point microwave links), radar systems, medical imaging (ultrasound), and industrial data acquisition. The dual-channel capability makes it ideal for diversity reception and I/Q demodulation, where two channels must be sampled simultaneously with matched performance.
When designing with the AD9268, ensure a clean, low-jitter clock source to achieve the specified SNR and SFDR. The analog input should be driven with a differential amplifier or balun to optimize performance, and the power supply pins should be decoupled with 0.1 uF and 10 uF capacitors. The device is available in a 64-lead LFCSP package, which provides excellent thermal performance and a compact footprint.
直接替换替代料： AD9268 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
AD9258
✅ 直接替换📋 参考替代料（不在目录中）
AD9251
✅ 直接替换📋 参考替代料（不在目录中）
AD9231
✅ 直接替换📋 参考替代料（不在目录中）
AD9204
✅ 直接替换📋 参考替代料（不在目录中）
SC9268
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
GX9268
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD9268 最大额定值与电气特性
| 分辨率 | 16 bits |
| Number of Channels | 2 (dual) |
| 采样率 | 80 MSPS / 105 MSPS / 125 MSPS |
| Input Type | Differential |
| Data Interface | Parallel CMOS / LVDS |
| 电源电压 | 1.8 V (analog), 1.8 V / 3.3 V (digital) |
| SNR | 78 dBFS (typical) |
| SFDR | 90 dBc (typical) |
| Power Dissipation | 1.2 W (typical at 125 MSPS) |
| 工作温度范围 | -40°C to +85°C |
| 封装 | 64-lead LFCSP (9x9 mm) |
| 安装类型 | Surface Mount |
| Reference Type | Internal / External |
| RoHS 状态 | Compliant |
| Pin Compatibility | AD9258, AD9251, AD9231, AD9204 |
AD9268 引脚配置
| 引脚 1 | AVDD — Analog power supply (1.8 V) |
| 引脚 2 | AVSS — Analog ground |
| 引脚 3 | VIN+ — Positive differential analog input |
| 引脚 4 | VIN- — Negative differential analog input |
| 引脚 5 | AVSS — Analog ground |
| 引脚 6 | SENSE — Reference mode selection |
| 引脚 7 | REF — Voltage reference output/input |
| 引脚 8 | AVDD — Analog power supply (1.8 V) |
| 引脚 9 | CLK+ — Positive differential clock input |
| 引脚 10 | CLK- — Negative differential clock input |
| 引脚 11 | AVSS — Analog ground |
| 引脚 12 | DRVDD — Digital output driver supply (1.8 V or 3.3 V) |
| 引脚 13 | DRVSS — Digital ground |
| 引脚 14 | D0A — Digital output bit 0 (Channel A) |
| 引脚 15 | D1A — Digital output bit 1 (Channel A) |
| 引脚 16 | D2A — Digital output bit 2 (Channel A) |
| 引脚 17 | D3A — Digital output bit 3 (Channel A) |
| 引脚 18 | D4A — Digital output bit 4 (Channel A) |
| 引脚 19 | D5A — Digital output bit 5 (Channel A) |
| 引脚 20 | D6A — Digital output bit 6 (Channel A) |
| 引脚 21 | D7A — Digital output bit 7 (Channel A) |
| 引脚 22 | D8A — Digital output bit 8 (Channel A) |
| 引脚 23 | D9A — Digital output bit 9 (Channel A) |
| 引脚 24 | D10A — Digital output bit 10 (Channel A) |
| 引脚 25 | D11A — Digital output bit 11 (Channel A) |
| 引脚 26 | D12A — Digital output bit 12 (Channel A) |
| 引脚 27 | D13A — Digital output bit 13 (Channel A) |
| 引脚 28 | D14A — Digital output bit 14 (Channel A) |
| 引脚 29 | D15A — Digital output bit 15 (Channel A) |
| 引脚 30 | DRVSS — Digital ground |
| 引脚 31 | DRVDD — Digital output driver supply |
| 引脚 32 | D0B — Digital output bit 0 (Channel B) |
| 引脚 33 | D1B — Digital output bit 1 (Channel B) |
| 引脚 34 | D2B — Digital output bit 2 (Channel B) |
| 引脚 35 | D3B — Digital output bit 3 (Channel B) |
| 引脚 36 | D4B — Digital output bit 4 (Channel B) |
| 引脚 37 | D5B — Digital output bit 5 (Channel B) |
| 引脚 38 | D6B — Digital output bit 6 (Channel B) |
| 引脚 39 | D7B — Digital output bit 7 (Channel B) |
| 引脚 40 | D8B — Digital output bit 8 (Channel B) |
| 引脚 41 | D9B — Digital output bit 9 (Channel B) |
| 引脚 42 | D10B — Digital output bit 10 (Channel B) |
| 引脚 43 | D11B — Digital output bit 11 (Channel B) |
| 引脚 44 | D12B — Digital output bit 12 (Channel B) |
| 引脚 45 | D13B — Digital output bit 13 (Channel B) |
| 引脚 46 | D14B — Digital output bit 14 (Channel B) |
| 引脚 47 | D15B — Digital output bit 15 (Channel B) |
| 引脚 48 | DRVSS — Digital ground |
| 引脚 49 | DRVDD — Digital output driver supply |
| 引脚 50 | PDWN — Power-down control (active high) |
| 引脚 51 | DFS — Data format select (offset binary / twos complement) |
| 引脚 52 | OEB — Output enable for Channel B (active low) |
| 引脚 53 | OEA — Output enable for Channel A (active low) |
| 引脚 54 | AVSS — Analog ground |
| 引脚 55 | AVDD — Analog power supply (1.8 V) |
| 引脚 56 | VREF — Voltage reference output |
| 引脚 57 | AVSS — Analog ground |
| 引脚 58 | AVDD — Analog power supply (1.8 V) |
| 引脚 59 | VIN+B — Positive differential analog input (Channel B) |
| 引脚 60 | VIN-B — Negative differential analog input (Channel B) |
| 引脚 61 | AVSS — Analog ground |
| 引脚 62 | AVDD — Analog power supply (1.8 V) |
| 引脚 63 | NC — No connect |
| 引脚 64 | EPAD — Exposed pad (thermal and ground) |
典型应用
AD9268 适用于 6 应用s: Communications Receivers, Radar Systems, Medical Imaging (Ultrasound), Industrial Data Acquisition, Test and Measurement, Wireless Infrastructure.
Communications Receivers
The AD9268's dual 16-bit channels and high sample rate up to 125 MSPS make it ideal for I/Q demodulation in cellular base stations and microwave links. Its 78 dBFS SNR and 90 dBc SFDR ensure excellent signal fidelity for multi-carrier reception. The device's pin compatibility with the AD9258 allows easy migration between 16-bit and 14-bit designs. In a typical receiver, the AD9268 digitizes the analog I and Q signals from the downconverter, enabling digital processing for channel filtering and demodulation. The high SFDR minimizes intermodulation distortion, which is critical in crowded spectrum environments. Power dissipation of 1.2 W is acceptable for base station equipment, and the small LFCSP package saves board space.
推荐
Radar Systems
In radar systems, the AD9268 provides high-speed dual-channel digitization for I/Q processing of return signals. Its 16-bit resolution and 125 MSPS sample rate capture fine amplitude and phase details, improving target detection and range resolution. The device's low noise and high SFDR are essential for distinguishing weak echoes from clutter. The dual channels enable simultaneous sampling of two polarizations or two antenna elements, enhancing system performance. The AD9268's wide operating temperature range (-40°C to +85°C) suits rugged military and aerospace environments. Its power dissipation is manageable with proper thermal design, and the LFCSP package is suitable for compact radar modules.
推荐
Medical Imaging (Ultrasound)
The AD9268 is well-suited for ultrasound systems, where dual-channel, high-resolution ADC conversion is required for beamforming and image processing. Its 16-bit resolution provides fine amplitude resolution for detecting subtle tissue differences, while the 125 MSPS sample rate supports high-frequency transducers. The device's low noise performance ensures clear images with minimal artifacts. The dual channels allow simultaneous processing of multiple transducer elements, improving frame rates. The AD9268's small package and low power consumption are advantageous for portable ultrasound devices. Its pin compatibility with other ADI ADCs offers design flexibility for different system configurations.
推荐
Industrial Data Acquisition
In industrial data acquisition systems, the AD9268 provides high-speed, high-resolution conversion for monitoring and control applications. Its dual channels enable simultaneous sampling of two signals, such as voltage and current, for power monitoring or motor control. The 16-bit resolution ensures accurate measurement of small signal variations, while the 125 MSPS sample rate captures fast transients. The device's robust design operates over a wide temperature range, making it suitable for harsh industrial environments. The AD9268's low power dissipation reduces thermal stress in enclosed systems. Its flexible digital interface (CMOS or LVDS) simplifies integration with FPGAs or DSPs.
推荐
Test and Measurement
The AD9268 is used in oscilloscopes, spectrum analyzers, and other test equipment requiring high-speed, high-resolution digitization. Its dual channels allow simultaneous acquisition of two signals, useful for differential measurements or two-channel scopes. The 16-bit resolution and 125 MSPS sample rate provide detailed waveform capture with high dynamic range. The device's low noise and high SFDR ensure accurate measurement of small signals in the presence of large ones. The AD9268's small package and low power consumption are beneficial for portable instruments. Its pin compatibility with other ADI ADCs allows designers to offer multiple product variants with minimal redesign.
推荐
Wireless Infrastructure
The AD9268 is ideal for wireless infrastructure such as small cells and remote radio heads (RRHs). Its dual 16-bit channels and high sample rate support multi-carrier GSM/WCDMA/LTE reception. The device's high SFDR and SNR ensure compliance with stringent spectral emission masks. The AD9268's low power consumption is critical for RRHs where heat dissipation is limited. Its small LFCSP package enables compact radio designs. The device's pin compatibility with the AD9258 allows a straightforward upgrade path from 14-bit to 16-bit resolution. The AD9268 also supports external reference operation for gain calibration, enhancing system flexibility.
推荐
推荐产品汇总
工程参考数据： AD9268 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD9258 | AD9251 | AD9231 | AD9204 | SC9268 | GX9268 |
|---|---|---|---|---|---|---|---|
| Package | 64-lead LFCSP | 64-lead LFCSP | 64-lead LFCSP | 64-lead LFCSP | 64-lead LFCSP | 64-lead LFCSP | 64-lead LFCSP |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | SGMC | GXSC |
| Resolution | 16 bits | 14 bits | 14 bits | 12 bits | 12 bits | 16 bits | 16 bits |
| Max Sample Rate | 125 MSPS | 125 MSPS | 40 MSPS | 40 MSPS | 40 MSPS | 125 MSPS | 125 MSPS |
| SNR | 78 dBFS | 74 dBFS | 74 dBFS | 70 dBFS | 70 dBFS | 78 dBFS | 78 dBFS |
| SFDR | 90 dBc | 88 dBc | 85 dBc | 82 dBc | 82 dBc | 90 dBc | 90 dBc |
| Power Dissipation | 1.2 W | 1.1 W | 0.5 W | 0.4 W | 0.4 W | 1.2 W | 1.2 W |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Pin Compatibility | Yes (with AD9258, AD9251, AD9231, AD9204) | Yes | Yes | Yes | Yes | Yes | Yes |
关键差异点
- 16-bit resolution with 125 MSPS sample rate （对比 AD9258)
- Pin-compatible with multiple ADI ADCs （对比 AD9251)
- High SFDR of 90 dBc （对比 AD9231)
设计说明
The AD9268 requires a clean 1.8 V analog supply (AVDD) and a separate digital supply (DRVDD) that can be 1.8 V or 3.3 V. Decouple each supply pin with a 0.1 uF ceramic capacitor placed as close as possible to the pin, and a 10 uF bulk capacitor on the board. Use a low-noise LDO for AVDD to minimize supply-induced noise, which can degrade SNR. The power dissipation of 1.2 W at 125 MSPS should be considered in thermal design; the exposed pad (EPAD) must be soldered to a ground plane for effective heat sinking.
For optimal performance, use a solid ground plane under the AD9268 and split analog and digital ground planes only if necessary, connecting them at a single point. The analog input traces should be routed as differential pairs with controlled impedance (typically 100 ohms differential) and kept as short as possible. Place the input drive amplifier (e.g., ADL5565) close to the ADC to minimize parasitic capacitance. The clock input should also be routed as a differential pair with 50-ohm single-ended impedance, and the clock source should have low jitter to achieve the specified SNR. Avoid routing digital output traces near the analog input to prevent coupling.
A common mistake is driving the analog input single-ended, which degrades SFDR and SNR. Always use a differential drive circuit, such as a balun or differential amplifier. Another pitfall is using a noisy clock source; the AD9268's SNR is directly affected by clock jitter, so use a low-jitter clock (e.g., from a crystal oscillator or a dedicated clock buffer like ADCLK905). Ensure the SENSE pin is correctly configured for the desired reference mode; leaving it floating may result in unexpected full-scale range. Also, do not exceed the absolute maximum ratings on any pin, especially the analog input, which could damage the device.
合规信息
RoHS compliant per Analog Devices product page. Not AEC-Q100 qualified; for automotive, consider AD9268-125EBZ evaluation board for testing.
