ADC10062CIWM/NOPB - 10-Bit 600ns Dual-Input ADC | Texas Instruments
料号： ADC10062CIWM/NOPB ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.92 | $8.92 |
| 10 | $8.04 | $80.40 |
| 100 | $7.18 | $718.00 |
| 500 | $6.42 | $3,210.00 |
| 1,000 | $5.85 | $5,850.00 |
ADC10062CIWM/NOPB 概述
An ADC (analog-to-digital converter) is a mixed-signal data converter that quantizes a continuous analog input voltage into a discrete digital code suitable for digital processing. Within the power management and signal chain hierarchy, ADCs sit between analog front ends (sensor + amplifier + filter) and a digital host (microcontroller, FPGA, or DSP). Flash ADCs and multistep variants such as the ADC10062 trade bit count and latency for very high conversion speed, making them well suited to embedded data acquisition where single-digit microsecond settling is acceptable.
Key features include two analog input channels with a built-in 2:1 multiplexer, an integrated track-and-hold that removes the need for an external SHA, a self-calibrating architecture that corrects linearity errors at power-up, and TTL/CMOS-compatible digital outputs. The wide SOIC-24 package (0.295 inch / 7.50 mm body width) eases hand-soldering and rework compared to narrow-body SOIC, which matters for legacy industrial designs.
Technically, the multistep architecture combines the speed advantages of flash conversion with the silicon efficiency of successive-approximation designs, yielding a sub-microsecond conversion at a power budget typically reserved for slower SAR ADCs. The differential non-linearity is rated at ±0.5 LSB and the integral non-linearity at ±1 LSB, adequate for process control and instrumentation front ends.
Typical applications include industrial process control loops, portable data loggers, multichannel instrumentation, and embedded system front ends where two analog signals (e.g., temperature + pressure) share one converter to reduce BOM cost and PCB area.
When designing with the ADC10062CIWM/NOPB, observe the datasheet layout guidance: keep analog and digital ground planes joined only at the AGND/DGND pin pair, decouple VCC close to the supply pin with a 0.1 uF ceramic plus a larger tantalum or electrolytic bulk cap, and buffer the analog input if the source impedance exceeds the recommended 1 kohm maximum.
This page synthesizes distributor stock levels, pin-compatible alternatives, and practical design notes not found in the standalone manufacturer datasheet, providing a single engineering reference for the ADC10062CIWM/NOPB.
直接替换替代料： ADC10062CIWM/NOPB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC10062CIWM/NOPB （相同外形与封装尺寸） ——差异在于 Architecture, Input Type, Package, Analog Supply Voltage, Data Interface.
快速对比工具——选择替代料号进行并排对比：
ADC10061CIWM/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC10061CIWM
✅ 直接替换📋 参考替代料（不在目录中）
ADC10062CIWM
✅ 直接替换📋 参考替代料（不在目录中）
ADC10064CIWM/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC10158CIWM
✅ 直接替换📋 参考替代料（不在目录中）
ADC0848BCN/NOPB
✅ 直接替换✓ 有现货
$5.4 / 个
查看数据手册 →ADC10062CIWM/NOPB 最大额定值与电气特性
| 分辨率 | 10 bits |
| Number of Analog Inputs | 2 (single-ended, 2:1 mux) |
| Architecture | Multistep (Flash-based, sub-microsecond) |
| Conversion Time | 600 ns typical |
| Maximum Sampling Rate | 800 kSPS (single-channel) |
| Analog Supply Voltage | +5 V typical (±5% per datasheet) |
| Power Dissipation | 235 mW maximum |
| Differential Non-Linearity (DNL) | ±0.5 LSB |
| Integral Non-Linearity (INL) | ±1 LSB |
| Sample-and-Hold | Integrated on-chip |
| Digital I/O Levels | TTL/CMOS compatible |
| Input Signal Range | 0 V to VREF (unipolar) |
| 工作温度范围 | -40 C to +85 C |
| 封装 | 24-SOIC wide (0.295 inch / 7.50 mm body) |
| Package Outline | SOIC-24 wide body, surface mount |
| 安装类型 | Surface Mount |
| MSL 等级 | 1 (unlimited floor life) |
| RoHS 状态 | Compliant (NOPB suffix) |
| 生命周期状态 | Obsolete - last-time-buy phase |
ADC10062CIWM/NOPB 引脚配置
| 引脚 1 | IN1 — Analog input 1 (mux channel 1) |
| 引脚 2 | IN2 — Analog input 2 (mux channel 2) |
| 引脚 3 | AGND — Analog ground |
| 引脚 4 | VREF — Reference voltage input |
| 引脚 5 | VCC — Analog +5V supply |
| 引脚 6 | DB0 — Data output bit 0 (LSB) |
| 引脚 7 | DB1 — Data output bit 1 |
| 引脚 8 | DB2 — Data output bit 2 |
| 引脚 9 | DB3 — Data output bit 3 |
| 引脚 10 | DB4 — Data output bit 4 |
| 引脚 11 | DB5 — Data output bit 5 |
| 引脚 12 | DB6 — Data output bit 6 |
| 引脚 13 | DB7 — Data output bit 7 |
| 引脚 14 | DB8 — Data output bit 8 |
| 引脚 15 | DB9 — Data output bit 9 (MSB) |
| 引脚 16 | DGND — Digital ground |
| 引脚 17 | OE — Output enable (active low) |
| 引脚 18 | CONVST — Conversion start input |
| 引脚 19 | EOC — End-of-conversion output |
| 引脚 20 | CAL — Calibration control |
| 引脚 21 | S/H — Sample-and-hold control |
| 引脚 22 | MUXSEL — Analog mux select (0=IN1, 1=IN2) |
| 引脚 23 | NC — Not connected |
| 引脚 24 | NC — Not connected |
典型应用
ADC10062CIWM/NOPB 适用于 6 应用s: Industrial Process Control Loop, Portable Battery Data Logger, Multichannel Instrumentation Front End, Embedded Microcontroller Analog Front End, Legacy Test and Measurement Equipment, Automotive Sensor Interface Module.
Industrial Process Control Loop
The ADC10062CIWM/NOPB suits closed-loop process control where two analog signals (e.g., a primary process variable and a redundant sensor) must be digitized at sub-microsecond rates. With its 600 ns conversion time and integrated 2:1 multiplexer, the part can alternate between two 4-20 mA-derived voltage signals at up to 800 kSPS aggregate throughput, enabling fast PID-loop feedback without an external SHA. Designers typically pair it with a precision op-amp front end and an FPGA or microcontroller that reads the parallel 10-bit output bus. Power dissipation of 235 mW maximum keeps the converter well within the thermal budget of a sealed DIN-rail module.
推荐
Portable Battery Data Logger
The ADC10062CIWM/NOPB enables a portable, battery-powered two-channel data logger that digitizes analog signals such as voltage and current in real time. Its 235 mW maximum dissipation keeps total system power low enough to operate from a 4-AA battery pack for hours, while the wide SOIC-24 package remains hand-solderable for prototype and low-volume production. The integrated sample-and-hold eliminates the need for an external SHA, shrinking the BOM and freeing PCB area for an SD-card slot or wireless module. Typical use is logging battery voltage and load current during portable device test cycles.
推荐
Multichannel Instrumentation Front End
A 24-pin SOIC wide footprint makes the ADC10062CIWM/NOPB easy to place on a through-hole or mixed-technology instrumentation board, and its 2:1 internal mux enables two measurement channels from a single converter. With 10-bit resolution and ±0.5 LSB DNL, the part provides adequate accuracy for benchtop multimeters and panel-meter designs measuring DC signals up to a few kHz bandwidth. The TTL/CMOS parallel output bus feeds directly into an 8-bit microcontroller port or an FPGA without glue logic. Designers typically add an op-amp low-pass filter and a precision reference to meet the datasheet's input-impedance and noise recommendations.
推荐
Embedded Microcontroller Analog Front End
Pairing the ADC10062CIWM/NOPB with a microcontroller or low-end FPGA provides a fast, parallel-output analog front end for embedded systems that lack a high-speed ADC. The 600 ns conversion time keeps total acquisition latency below 1 microsecond, which is sufficient for motor-control current sensing and encoder feedback in industrial drives. The 10-bit resolution matches typical inverter current-sense accuracy requirements and avoids the cost of a 12- or 14-bit ADC. The integrated sample-and-hold and 2:1 mux reduce component count versus a discrete SAR + external SHA + analog switch design.
推荐
Legacy Test and Measurement Equipment
The ADC10062CIWM/NOPB remains in service in legacy oscilloscopes, spectrum analyzers, and waveform digitizers originally designed in the late 1990s and early 2000s, where its 600 ns conversion time and 10-bit resolution fit the front-end digitizer slot. Replacement boards for field service use the same SOIC-24 wide footprint to avoid mechanical rework on existing test fixtures. The /NOPB suffix confirms RoHS compliance for newer EU-bound spares stock. Engineers maintaining legacy equipment rely on the part's stable electrical characteristics across production lots.
推荐
Automotive Sensor Interface Module
Although not AEC-Q100 qualified itself, the ADC10062CIWM/NOPB has been used in non-safety automotive subsystems such as HVAC climate sensors and body-controller analog inputs where the -40 C to +85 C industrial temperature range is acceptable. The 2:1 internal mux allows a single converter to digitize both a cabin temperature sensor and a humidity sensor, reducing BOM cost and PCB area. The 800 kSPS maximum sampling rate is far above what HVAC or body-control applications require, providing headroom for additional digital filtering. Designers must verify the obsolete lifecycle status against their product's expected service life before committing to new automotive designs.
推荐
推荐产品汇总
工程参考数据： ADC10062CIWM/NOPB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC10061CIWM/NOPB | ADC10064CIWM/NOPB | ADC10158CIWM |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 24-SOIC wide | 24-SOIC wide - same | 24-SOIC wide - same | 24-SOIC wide - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits |
| Number of Analog Inputs | 2 (2:1 mux) | 1 (single-channel) | 8 (8:1 mux) | 8 (8:1 mux) |
| Conversion Time | 600 ns | 600 ns | 600 ns | ~1 us |
| Sampling Rate (max) | 800 kSPS | 800 kSPS | 800 kSPS | ~500 kSPS |
| Architecture | Multistep flash | Multistep flash | Multistep flash | Half-flash |
| Power Dissipation (max) | 235 mW | 235 mW | 235 mW | ~250 mW |
| Integrated Sample-and-Hold | Yes | Yes | Yes | Yes |
| RoHS Compliance | Yes (NOPB) | Yes (NOPB) | Yes (NOPB) | Confirm variant |
关键差异点
- Integrated 2:1 analog multiplexer with on-chip sample-and-hold （对比 ADC10061CIWM/NOPB)
- Sub-microsecond conversion at 235 mW power budget （对比 ADS7883 (modern SAR))
- Wide SOIC-24 package for hand-soldering and rework （对比 ADS7883 (MSOP-8))
设计说明
Use a star-ground topology with AGND and DGND joined only at the chip's AGND/DGND pins. Place a 0.1 uF ceramic decoupling capacitor and a 10 uF tantalum (or larger electrolytic) bulk capacitor within 5 mm of the +VCC pin. Keep analog input traces short and routed away from the parallel digital output bus (DB0-DB9) to minimize digital noise coupling into the analog front end.
If the analog source impedance exceeds 1 kohm, buffer the input with a low-noise op-amp (e.g., OPA2277 or OPA1612). The ADC10062CIWM/NOPB samples the input at the rising edge of CONVST, so settle the analog input to within ±0.5 LSB before triggering conversion. Add a 100 ohm series resistor at each analog input pin to dampen ringing when driving from a long cable or capacitive source.
Do not exceed the absolute maximum analog input voltage of VCC + 0.3 V or fall below AGND - 0.3 V - the ESD diodes will forward-conduct and damage the part. Ensure CONVST pulse width meets the minimum specified in the datasheet (typically 50 ns); a too-narrow pulse may not trigger conversion. The OE pin must be held low to enable the output bus; floating OE leaves the outputs in a high-Z state.
Estimated: at +5 V supply and 235 mW dissipation, the +5 V supply pin draws approximately 47 mA. Add a ferrite bead in series with the analog supply if the +5 V rail is shared with switching converters. Power-supply rejection can be improved by placing a 10 ohm resistor between the bulk capacitor and the IC supply pin.
合规信息
RoHS and REACH compliance indicated by /NOPB suffix on the TI part number. The /NOPB version replaces legacy lead-bearing variants; halogen-free status not explicitly stated in the datasheet excerpt available.
