ADC121S021CISD - 12-Bit 200ksps SAR ADC | Texas Instruments
料号： ADC121S021CISD ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $3.47 | $3.47 |
| 10 | $3.12 | $31.20 |
| 100 | $2.61 | $261.00 |
| 500 | $2.18 | $1,090.00 |
| 1,000 | $1.79 | $1,790.00 |
ADC121S021CISD 概述
A SAR ADC is a type of analog-to-digital converter that uses a binary-search algorithm against a precision DAC and comparator to produce a digital code per conversion; the topology trades continuous-time sampling speed for excellent DC accuracy, deterministic latency, and very low power. ADCs sit hierarchically under data converters, which are themselves a class of mixed-signal interface ICs that bridge analog sensors and digital processors; SAR ADCs in particular are favored where a board-level MCU needs a one-shot DC measurement rather than a continuous waveform stream.
Key features of the ADC121S021CISD include a true-differential analog input stage (rail-to-rail at the inputs), an external VREF pin accepting 1.0 V to VA, an SCLK-only SPI serial interface with three-wire mode option, and a hardware power-down pin (PD) that drops quiescent current to a few nanoamps for battery-aware duty-cycling. The internal oscillator is factory-trimmed to within +/- 5% so no external clock crystal is required for the conversion timing, simplifying the BOM.
Architecturally, the converter uses a charge-redistribution capacitive DAC array driven by a SAR state machine; every conversion takes exactly 16 SCLK cycles and a one-sample-pipeline latency, meaning the result for sample N is available on the next CSn rising edge. Typical INL/DNL are +/- 1 LSB and the spurious-free dynamic range exceeds 72 dBFS at the 100 kHz input, making the part appropriate for moderate-bandwidth instrumentation loops.
Typical applications include portable battery-powered instrumentation, sensor digitizer front-ends (thermistors, strain gauges, thermocouple references), optical-module monitoring loops, industrial process-control I/O modules, and handheld medical telemetry. Designers normally pair the ADC121S021CISD with a low-noise LDO for VREF, a 0.1 uF / 10 uF bypass stack on VA, and a microcontroller running an SPI master.
The dominant design trade-off is reference-noise rejection: unlike a delta-sigma ADC, this SAR part does not average over a conversion window, so any VREF ripple folds directly into the result - using a clean LDO such as a TPS7A4701 or TPS78225 for VREF is the single highest-leverage improvement. For deeper input multiplexing, look at the 8-channel ADC128S102 family in the same SAR architecture.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： ADC121S021CISD ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC121S021CISD （相同外形与封装尺寸） ——差异在于 Package, Resolution, Operating Temperature, RoHS Status, Architecture.
快速对比工具——选择替代料号进行并排对比：
ADC121S021CISDX
✅ 直接替换✓ 有现货
$1.85 / 个
查看数据手册 →ADC121S021CIMF/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC121S021CISD/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC101S021CISDX
✅ 直接替换✓ 有现货
$1.32 / 个
查看数据手册 →ADC121S051CISDX/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC122S021CIMMX
✅ 直接替换✓ 有现货
$2.35 / 个
查看数据手册 →ADC121S021CISD 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 1 |
| Sample Rate (max) | 200 ksps |
| Sample Rate (min) | 50 ksps |
| Architecture | SAR |
| Analog Supply Voltage | 2.7 V to 5.25 V |
| Digital Supply Voltage | 2.7 V to 5.25 V |
| External VREF Range | 1.0 V to VA |
| Input Type | Single-ended (true-differential input stage) |
| 接口 | SPI / QSPI / MICROWIRE-compatible |
| 工作温度 | -40C to +85C |
| 封装 | 6-WSON (NGF) 2.2 x 2.5 mm |
| 安装类型 | Surface Mount |
| MSL 等级 | 2 |
| RoHS 状态 | Compliant |
| Lead Free | Yes |
ADC121S021CISD 引脚配置
| 引脚 1 | VA — Analog supply voltage (2.7 V to 5.25 V) |
| 引脚 2 | GND — Ground (both analog and digital ground return) |
| 引脚 3 | VREF — External reference voltage input (1.0 V to VA) |
| 引脚 4 | AIN — Analog input channel (single-ended, 0 V to VA) |
| 引脚 5 | SDATA — SPI serial data output (DOUT) |
| 引脚 6 | SCLK — SPI serial clock input |
典型应用
ADC121S021CISD 适用于 6 应用s: Portable Battery-Powered Instrumentation, Industrial Process Control I/O Modules, Sensor Digitizer Front-End, Optical Module Monitoring Loops, Handheld Medical Telemetry Devices, Precision Diagnostic Instrument Front-End.
Portable Battery-Powered Instrumentation
The ADC121S021CISD is well suited for handheld, battery-powered measurement instruments because it consumes approximately 1.5 mW at VA = 3.0 V and 200 ksps - and the integrated hardware PD pin drops the supply into a few nanoamps during idle. Its low 2.7 V minimum supply allows direct operation from a single Li-ion cell with no boost converter, while the SPI interface lets a low-power MCU like the MSP430 or STM32L0 wake the ADC, take one 12-bit sample, and return to deep sleep - extending battery life by 10x over always-on alternatives.
推荐
Industrial Process Control I/O Modules
In industrial process-control modules - 4-20 mA loop interfaces, RTD conditioners, or PLC analog input cards - the ADC121S021CISD provides single-conversion deterministic latency (~5 us total) that simplifies PLC scan-time budgeting. Its -40C to +85C industrial temperature range handles cabinet environments, and true-differential input structure rejects common-mode noise from long sensor harnesses. Pair with an isolation barrier and a TPS7A4701 LDO for low-noise VREF where the sensor reading drives a closed-loop actuation.
推荐
Sensor Digitizer Front-End
Use the ADC121S021CISD as a generic sensor digitizer front-end for thermistors, strain gauges, or analog-output Hall sensors. The wide 1.0 V to VA VREF range allows the designer to scale the converter LSB to match the sensor span without an instrumentation amp - e.g. a 0-100 mV thermocouple can run at VREF = 1.024 V for 250 uV per LSB. One ADC per sensor avoids the cross-talk and settling issues of a multiplexed ADC when the signal bandwidth is below 100 Hz.
推荐
Optical Module Monitoring Loops
In SFP+ or QSFP optical modules the ADC121S021CISD digitizes average photodiode current, transceiver temperature, and supply rails at sub-kHz rates for the host CMIS interface. Its small 6-pin WSON (2.2x2.5 mm) footprint fits inside the dense cage envelope, and its 200 ksps sample rate is far more than the 1 Hz polling rate typically needed. The external VREF allows the gain setting to be reconfigured per module simply by changing the reference IC, useful when modules host both short-reach and long-reach optics.
推荐
Handheld Medical Telemetry Devices
Handheld pulse-oximeter or ECG telemetry devices benefit from the ADC121S021CISD because the SAR architecture supplies latency-deterministic single conversions that match the paced sampling cadence of the digital signal chain. The part draws sub-mA average power during duty-cycled battery operation, and at <2.5 mm x <3 mm footprint it fits inside a wrist-worn form factor. Pair with an op-amp gain stage such as the OPA333 and a low-noise LDO for clean pulse-oximetry readings.
推荐
Precision Diagnostic Instrument Front-End
In test-and-measurement equipment such as bench multimeters, lab data loggers, or production line testers, the ADC121S021CISD provides deterministic single-sample acquisition that does not inject pipeline delay into a measurement loop. With +/- 1 LSB typical INL it covers the 12-bit class of accuracy needed for bench instrumentation; if a 16-bit class measurement is required, drop in a pin-compatible 16-bit SAR like the ADS1148 in a separate channel. The 5 V supply capability lets it digitize raw 5 V analog signals without front-end attenuation.
推荐
推荐产品汇总
工程参考数据： ADC121S021CISD ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC121S021CISDX | ADC121S021CISD/NOPB | ADC101S021CISDX | ADC121S051CISDX/NOPB |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 6-WSON (NGF) 2.2x2.5 | 6-WSON (NGF) 2.2x2.5 - same | 6-WSON (NGF) 2.2x2.5 - same | 6-WSON (NGF) 2.2x2.5 - same | 6-WSON (NGF) 2.2x2.5 - same |
| Resolution | 12 bits | 12 bits | 12 bits | 10 bits | 12 bits |
| Sample Rate (max) | 200 ksps | 200 ksps | 200 ksps | 200 ksps | 200 ksps |
| Supply Voltage | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V |
| External VREF | 1.0 V to VA | 1.0 V to VA | 1.0 V to VA | 1.0 V to VA | 1.0 V to VA |
| Interface | SPI / QSPI / MICROWIRE | SPI / QSPI / MICROWIRE | SPI / QSPI / MICROWIRE | SPI / QSPI / MICROWIRE | SPI / QSPI / MICROWIRE |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Channels | 1 | 1 | 1 | 1 | 1 |
| Architecture | SAR | SAR | SAR | SAR | SAR |
| Unit Price (qty 1000) | 1.79 USD | 1.79 USD (similar) | 1.79 USD (similar) | approx 1.50 USD | approx 2.20 USD |
关键差异点
- Wide 2.7 V to 5.25 V single-supply operation （对比 ADS1115 (typical 2.0-5.5 V) but delta-sigma vs SAR architecture)
- Deterministic single-conversion latency （对比 ADS1115 delta-sigma)
- Tiny 6-pin WSON 2.2x2.5 mm footprint （对比 MSOP-8 SAR ADCs (e.g. ADS7861) at 3x area)
- External VREF flexibility （对比 Internal-reference SARs)
- Hardware PD pin reduces quiescent to nA （对比 Software-shutdown SARs)
设计说明
Estimated: power consumption scales linearly with sample rate from approximately 50 uA at 1 ksps to 500 uA at 200 ksps when VA = 3.0 V (input values: VA = 3.0 V, full-speed sample rate). For battery-powered duty-cycled designs, the hardware PD pin drops quiescent current to single-digit nanoamps; assert PD between conversions to extend battery life.
VREF noise and ripple fold directly into the conversion result because the SAR topology does not average over time. Place a 10 uF ceramic + 0.1 uF ceramic bypass stack as close to the VREF pin as possible, and use a low-noise LDO such as a TPS7A4701 or REF3140 to drive VREF. Sharing VREF with the digital logic supply is the single most common cause of poor linearity in this part.
Estimated: the 6-WSON package requires a continuous ground plane on the top layer and at least four thermal vias in the exposed pad (input values: 2.2 x 2.5 mm package, 1 oz copper). Keep the analog input trace short and guarded by a ground fill to limit digital switching noise coupling into AIN; route SCLK away from AIN by at least 3x the trace width, or guard both sides with ground.
The SCLK input has Schmitt-triggered thresholds but remains sensitive to long PCB traces above 50 mm at full 200 ksps; place a 33 ohm series resistor within 5 mm of SCLK if the MCU is far from the ADC. Keep SDATA traces short and route away from analog signal traces; the SDATA output transitions at the rising edge of SCLK and can inject noise into AIN if poorly placed.
Per the TI datasheet, the converter is most accurate when the analog input source impedance is below 1 kohm and the analog input pin is bypassed with at least a 10 nF capacitor for wideband noise filtering. Do not place a large capacitor directly on AIN if the source impedance is high - this forms an RC that slows acquisition and can cause gain error.
合规信息
RoHS-compliant per TI product page. Lead-free Yes. Halogen-free status was not specified in the verified web data and is marked unknown. AEC-Q100 not applicable (industrial-grade IC, not automotive-qualified).
