ADC122S101CIMM - 12-Bit 1MSPS 2-Ch SAR ADC | Texas Instruments
料号： ADC122S101CIMM ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $3.62 | $3.62 |
| 10 | $3.18 | $31.80 |
| 100 | $2.71 | $271.00 |
| 500 | $2.3 | $1,150.00 |
| 1,000 | $1.96 | $1,960.00 |
ADC122S101CIMM 概述
An SAR ADC is a type of data converter that uses a binary search through successive test voltages to resolve the input voltage into a digital code, with one conversion cycle per clock. SAR ADCs are favored over delta-sigma and pipeline types when low latency, deterministic sampling, and compact package size are priorities - placing them in the hierarchy of data converters (SAR ADC -> ADC -> data converter IC -> signal chain -> mixed-signal semiconductor).
Key features include guaranteed 12-bit resolution across the 500 ksps to 1 MSPS sample-rate range, low power consumption of approximately 1.4 mW at 1 MSPS with a 3 V supply, an internal 2.5 V reference, and an operating temperature range of -40 °C to +85 °C. The device uses a pseudo-differential input topology and integrates an input track-and-hold amplifier to support AC input signals beyond the Nyquist bandwidth.
The architecture pairs a charge-redistribution capacitive DAC with a high-speed comparator and SAR control logic. Conversion results are clocked out MSB-first on the falling edge of SCLK through a single DOUT pin, with a chip-select (CS) pin enabling multi-device SPI bus sharing.
Typical applications include portable instrumentation, motor control feedback loops, optical sensor digitizers (photodiodes, position encoders), consumer audio front ends, and industrial process-control analog front ends. The combination of low power, small footprint, and SPI compatibility makes it suitable for micro-controller-based designs where PCB area and software simplicity are at a premium.
When designing with this device, allocate a 1 ms acquisition time and at least a 10 nF decoupling capacitor on AVDD; also tie unused analog inputs to AVDD or AGND to avoid floating-input bias-current drift and degraded noise performance.
This page synthesizes distributor pricing, drop-in same-family and same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： ADC122S101CIMM ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC122S101CIMM （相同外形与封装尺寸） ——差异在于 Package, Input Type, RoHS Status, Number of Channels, Digital Interface.
快速对比工具——选择替代料号进行并排对比：
ADC122S101CIMM/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC122S101CIMMX
✅ 直接替换📋 参考替代料（不在目录中）
ADC122S051CIMMX
✅ 直接替换✓ 有现货
$2.99 / 个
查看数据手册 →ADC122S021CIMMX
✅ 直接替换✓ 有现货
$2.35 / 个
查看数据手册 →ADC102S101CIMMX/NOPB
✅ 直接替换✓ 有现货
$2.1 / 个
查看数据手册 →ADC122S101CIMM 最大额定值与电气特性
| 分辨率 | 12 bit |
| Number of Channels | 2 |
| Sample Rate (max) | 1 MSPS |
| Sample Rate (min) | 500 kSPS |
| Architecture | SAR |
| Input Type | Single-Ended |
| 接口 | SPI / SSI serial |
| Analog Supply Voltage | 3 V to 5.25 V |
| Digital Supply Voltage | 2.7 V to 5.25 V |
| 输入电压范围 | 0 V to VA (5 V) |
| Internal Reference | 2.5 V |
| Power Dissipation (typ @ 3V) | 1.4 mW at 1 MSPS |
| 工作温度 | -40 °C to +85 °C |
| 封装 | 8-VSSOP (DGK) 3 mm × 3 mm |
| 安装类型 | Surface Mount |
| MSL 等级 | 1 (unlimited) |
| RoHS 状态 | Compliant |
| Screening Level | Industrial |
ADC122S101CIMM 引脚配置
| 引脚 1 | AIN1 — Analog input channel 1 (single-ended, 0-VA range) |
| 引脚 2 | AGND — Analog ground reference |
| 引脚 3 | VA — Analog supply voltage (3 V to 5.25 V) |
| 引脚 4 | VA / REF — Analog supply / internal 2.5 V reference decoupling |
| 引脚 5 | GND — Digital / substrate ground |
| 引脚 6 | DIN — Serial data input (CS-active daisy-chain mode) |
| 引脚 7 | SCLK — Serial clock input (max 25 MHz) |
| 引脚 8 | DOUT — Serial data output / chip-select input |
典型应用
ADC122S101CIMM 适用于 6 应用s: Portable Multi-Channel Sensor Digitization, Brushless DC Motor Phase-Current Feedback, Optical Encoder and Photodiode Front End, Industrial Process-Control Analog Front End, Consumer Audio Front-End Digitization, Medical Vital-Sign Monitoring Front End.
Portable Multi-Channel Sensor Digitization
The ADC122S101CIMM's 1 MSPS maximum sample rate and dual single-ended input channels make it a strong match for portable sensor hubs that digitize multiple analog transducers with one IC. Each channel can be sampled at 500 kSPS, well above the bandwidth of typical pressure, temperature, or strain-gauge signals. Combined with 1.4 mW typical dissipation at 3 V and an 8-VSSOP 3 mm x 3 mm footprint, the device extends battery life while freeing board area. Placed beside the MCU with a single SPI CS line, it replaces two slower ADCs while keeping the bus arbitration simple. Compared with delta-sigma ADCs, the SAR architecture avoids digital filter group delay, simplifying time-correlated sampling of fast sensors.
推荐
Brushless DC Motor Phase-Current Feedback
FOC motor controllers demand deterministic, low-latency analog-to-digital conversion at 100 kSPS to 1 MSPS to sample phase currents every PWM cycle. The ADC122S101CIMM's SAR architecture delivers one conversion per SCLK cycle and requires no digital filter settling time, giving precise timing alignment between the comparator and the ADC waveform. Two channels allow sensing of two phase currents simultaneously, with the third current reconstructible by Kirchhoff's law, eliminating an external current-sense amplifier in some designs. Its 12-bit resolution is well matched to current-loop control bandwidth, and the 8 VSSOP package drops directly onto compact motor-control PCBs.
推荐
Optical Encoder and Photodiode Front End
Position encoders and photodiode linear arrays produce baseband analog signals requiring sub-microsecond digitizing without latency or filter delay. The ADC122S101CIMM delivers 1 MSPS SAR sampling in a tiny 8-VSSOP footprint, capturing both channels of a quadrature optical sensor at 500 kSPS each. The single-ended 0-5 V input matches the output range of typical photodiode transimpedance amplifiers (TIAs) like the OPA2320. The 2.5 V internal reference keeps bill-of-materials cost low, while the 1.4 mW dissipation allows deployment in enclosed optical modules with minimal thermal drift.
推荐
Industrial Process-Control Analog Front End
Distributed control systems and 4-20 mA loop analog front ends require 12-bit precision and isolated digital interfaces to the controller. The ADC122S101CIMM's 12-bit guaranteed no-missing-codes, 1 MSPS throughput, and SPI serial output simplify optical isolation by requiring only four digital lines (CS, SCLK, DIN, DOUT). Two channels accommodate redundant or differential-pressure sensors sharing one converter. Operating from a single 5 V analog supply typical in industrial instrumentation, the device replaces more expensive isolation-grade ADCs when galvanic isolation is implemented at the digital SPI interface instead.
推荐
Consumer Audio Front-End Digitization
Audio front-end digitization often involves stereo-pair analog inputs sampled at moderate rates. The ADC122S101CIMM's dual single-ended channels with 1 MSPS throughput per device make it a viable 12-bit stereo sampler up to 500 kSPS per channel - far above audio Nyquist for 24-bit/96 kHz audio oversampling ratios, allowing time-domain averaging for SNR improvement. The 8-VSSOP package is smaller than typical audio-grade ADCs and fits into compact USB audio interfaces. However, for audiophile applications, a dedicated audio ADC like the PCM1803A provides higher dynamic range; the ADC122S101 is better suited for general-purpose mixed-signal boards where size and BOM cost matter more.
推荐
Medical Vital-Sign Monitoring Front End
Wearable pulse-oximeter and ECG monitoring devices sample photodiode currents and biopotential electrodes at low frequencies but require low-power, small-footprint ADCs with deterministic sampling. The ADC122S101CIMM provides 12-bit resolution at up to 1 MSPS, supporting both pulse-oximetry (sampling at ~500 Hz with high oversampling for noise reduction) and ECG (500 Hz to 1 kSPS sampling). The 1.4 mW power consumption preserves battery life in wrist-worn wearables, and the 3 mm x 3 mm 8-VSSOP footprint allows PCB integration alongside the BLE SoC and front-end analog conditioning stage. AEC-Q100 qualification is not available, so for medical-automotive applications consider other TI AEC-Q100-grade ADCs.
推荐
推荐产品汇总
工程参考数据： ADC122S101CIMM ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC122S101CIMM/NOPB | ADC122S101CIMMX | ADC122S051CIMMX | ADC122S021CIMMX | ADC102S101CIMMX/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 8-VSSOP (DGK) | 8-VSSOP (DGK) - same | 8-VSSOP (DGK) - same | 8-VSSOP (DGK) - same | 8-VSSOP (DGK) - same | 8-VSSOP (DGK) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 10 bit |
| Sample Rate (max) | 1 MSPS | 1 MSPS | 1 MSPS | 500 kSPS | 200 kSPS | 1 MSPS |
| Number of Channels | 2 single-ended | 2 single-ended | 2 single-ended | 2 single-ended | 2 single-ended | 2 single-ended |
| Architecture | SAR | SAR | SAR | SAR | SAR | SAR |
| Analog Supply Voltage | 3 V to 5.25 V | 3 V to 5.25 V | 3 V to 5.25 V | 3 V to 5.25 V | 3 V to 5.25 V | 3 V to 5.25 V |
| Lead-Free / RoHS | No (CIMM = matte-tin lead-bearing) | Yes (NOPB = lead-free RoHS) | Yes | Yes | Yes | Yes (NOPB) |
关键差异点
- Higher sample rate than the S051 family member （对比 ADC122S051CIMMX)
- Higher resolution than the 102 family member （对比 ADC102S101CIMMX/NOPB)
- Two single-ended inputs in a single 8-VSSOP （对比 Single-channel 8-VSSOP SAR ADCs)
设计说明
Estimated: Decouple AVDD with a 1 µF X7R ceramic capacitor within 5 mm of pin 3 (VA), and place a 0.1 µF X7R bypass on pin 4 (VA/REF). For 3 V analog supply operation, total power dissipation at 1 MSPS is approximately 1.4 mW, and at 5 V supply it rises to about 4 mW. Estimated thermal rise with the 8-VSSOP package (theta_JA ≈ 200 °C/W) is below 1 °C - no heatsink needed. If using the 2.5 V internal reference, attach an external 1 µF + 0.1 µF decoupling stack to VA/REF and avoid injecting switching currents on this pin.
Route the SPI bus (CS, SCLK, DIN, DOUT) on a single inner layer over a continuous ground plane, and keep traces shorter than 50 mm to minimize capacitive loading. Place the AGND pin 2 and GND pin 5 directly to the ground plane with via stitching. The exposed bottom pad of the 8-VSSOP package is not electrically connected and should be soldered to the ground pad for thermal dissipation, but no internal bond wire is present. Keep analog input traces routed away from digital SPI lines or shielded with a ground-stitch fence to avoid crosstalk.
Do not leave unused analog inputs floating - tie AIN2 (when channel 1 only is used) to AGVD/AGND to prevent input bias-current drift and degraded THD. Per TI datasheet, the device requires a minimum of 14 SCLK cycles to complete one conversion; if the host MCU's SPI peripheral emits only 8 SCLK cycles, configure a 16-bit or longer SPI frame to avoid mid-conversion abort. For applications requiring 16-bit data capture (e.g. averaging), append two zero SCLK edges to capture the lead-out data. Do not exceed 25 MHz SCLK rate; use series resistors (33 Ω) at SCLK output to dampen reflections in long traces.
The SAR converter's input bandwidth is wide enough to alias out-of-band noise into the baseband - place an anti-aliasing RC filter (R = 50 Ω to 100 Ω, C = 1 nF) at each transmission line input pin with -3 dB cutoff of 1.6 MHz to 3.2 MHz, well below the 1 MSPS Nyquist. This filter also isolates the converter's switched-capacitor input from the upstream op-amp output, preventing kickback-induced distortion. If driving the input directly from a high-output-impedance sensor, buffer with a low-noise CMOS op-amp like the OPA2320 to maintain linearity.
合规信息
CIMM suffix indicates matte-tin (lead-bearing) finish - RoHS non-compliant by exemption only. For lead-free RoHS, choose the ADC122S101CIMM/NOPB variant. Halogen-free per TI product page. Not AEC-Q100 qualified; not applicable for industrial-grade ADC. REACH and conflict-mineral reporting compliant per TI policy.
