ADC12D040CIVSX/NOPB - 12-Bit 40MSPS Dual A/D Converter | TI
料号： ADC12D040CIVSX/NOPB ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.85 | $328.50 |
| 100 | $29.2 | $2,920.00 |
| 500 | $25.95 | $12,975.00 |
| 1,000 | $23.1 | $23,100.00 |
ADC12D040CIVSX/NOPB 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and outputs a discrete digital code per sample, forming the critical bridge between the analog front end (sensors, transducers, RF stages) and the digital signal-processing back end (DSP, FPGA, microcontroller). The pipelined architecture family, to which the ADC12D040 belongs, interleaves low-resolution flash sub-stages with sample-and-hold residue amplifiers to deliver tens-of-MHz conversion rates at moderate (10-14 bit) resolution while keeping per-sample power significantly lower than full-flash architectures.
Key headline specifications include 12-bit resolution, 40 MSPS sampling rate per channel (two independent channels), 600 mW typical power consumption, internal or external voltage reference, and on-chip sample-and-hold on each input. The pipelined architecture produces a fixed deterministic latency and supports simultaneous sampling on both channels, which is essential for quadrature (I/Q) signal processing.
On the digital side, separate analog (AVDD) and driver (DRVDD) supply pins allow the parallel CMOS output bus to swing between 2.4V and the analog rail, simplifying connection to 1.8V-3.3V FPGA banks without level shifters. The integrated sample-and-hold and input multiplexer (single-ended or differential) relax analog front-end design.
Typical applications include digital oscilloscopes and waveform digitizers, communications receivers and IF sampling stages, medical imaging front ends, CCD/CIS imaging digitizers, and radar/sonar baseband acquisition. The dual-channel synchronous operation also suits multi-antenna diversity receivers where matched timing matters.
When designing with this part, allocate a continuous ground-return path under the analog input traces and place the 0.1 uF + 10 uF decoupling combination within 3 mm of each AVDD pin. Drive the analog inputs in true differential mode whenever possible; this maximizes SFDR and minimizes even-order distortion that directly limits ADC dynamic range.
This page synthesizes distributor pricing, drop-in tape-and-reel packaging alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： ADC12D040CIVSX/NOPB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC12D040CIVSX/NOPB （相同外形与封装尺寸） ——差异在于 Architecture, Digital Output Interface, Number of Channels, Operating Temperature Range, Package.
快速对比工具——选择替代料号进行并排对比：
ADC12D040CIVS/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12D065CIVSX/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12D100CIVSX/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12D040CIVSX
✅ 直接替换📋 参考替代料（不在目录中）
ADC12040CIVY
✅ 直接替换✓ 有现货
$5.52 / 个
查看数据手册 →ADC12D040CIVSX/NOPB 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (per channel) | 40 MSPS |
| Architecture | Pipelined CMOS with on-chip sample-and-hold |
| Analog Supply Voltage (AVDD) | +3.3 V nominal (single supply) |
| Digital I/O Supply (DRVDD) | 2.4 V to AVDD |
| Typical Power Dissipation | 600 mW |
| Reference | Internal or external (selectable) |
| Input Configuration | Single-ended or differential (selectable) |
| Digital Output Interface | Parallel CMOS, two's complement / straight binary |
| 工作温度范围 | -40 C to +85 C |
| 封装 | 64-TQFP (10x10 mm, 0.5 mm pitch) |
| 安装类型 | Surface Mount |
| Packaging | Tape & Reel (TR) |
| RoHS 状态 | Compliant |
| Product Origin | Originally National Semiconductor, now Texas Instruments |
ADC12D040CIVSX/NOPB 引脚配置
| 引脚 1 | VA1 — Analog supply for channel 1 |
| 引脚 2 | AIN1+ — Channel 1 analog input, positive (single-ended or differential) |
| 引脚 3 | AIN1- — Channel 1 analog input, negative (used in differential mode; ground in single-ended mode) |
| 引脚 4 | GND — Analog ground |
| 引脚 5 | VREF — Voltage reference (bypass pin, internal reference decoupling) |
| 引脚 6 | REFT — Reference decoupling top (bypass to GND with 10 uF / 0.1 uF) |
| 引脚 7 | REFB — Reference decoupling bottom (bypass to GND with 10 uF / 0.1 uF) |
| 引脚 8 | VA2 — Analog supply for channel 2 |
| 引脚 9 | AIN2+ — Channel 2 analog input, positive |
| 引脚 10 | AIN2- — Channel 2 analog input, negative |
| 引脚 11 | GND — Analog ground |
| 引脚 12 | DFS — Data format select (two's complement / straight binary) |
| 引脚 13 | SEN — Sample enable / input range select |
| 引脚 14 | PD — Power-down input (active high) |
| 引脚 15 | CLK+ — Differential clock input, positive |
| 引脚 16 | CLK- — Differential clock input, negative |
| 引脚 17 | GND — Digital ground / analog ground split |
| 引脚 18 | VD1 — Digital driver supply (DRVDD) for output drivers |
| 引脚 19 | D0 — Digital output bit 0 (LSB) |
| 引脚 20 | D1 — Digital output bit 1 |
| 引脚 21 | D2 — Digital output bit 2 |
| 引脚 22 | D3 — Digital output bit 3 |
| 引脚 23 | D4 — Digital output bit 4 |
| 引脚 24 | D5 — Digital output bit 5 |
| 引脚 25 | D6 — Digital output bit 6 |
| 引脚 26 | D7 — Digital output bit 7 |
| 引脚 27 | D8 — Digital output bit 8 |
| 引脚 28 | D9 — Digital output bit 9 |
| 引脚 29 | D10 — Digital output bit 10 |
| 引脚 30 | D11 (MSB) — Digital output bit 11 (MSB) |
| 引脚 31 | DRVDD — Digital output driver supply (2.4 V to AVDD) |
| 引脚 32 | DGND — Digital ground |
| 引脚 33 | DCSET / OTR — DC-set / out-of-range output (per datasheet) |
| 引脚 34 | OEN — Output enable (active low) for digital bus |
| 引脚 35 | MODE — Mode select for single-channel / dual-channel operation |
| 引脚 36 | VA_DRIVE — Driver analog supply pin |
| 引脚 37 | CAL — Calibration pin (initiate self-calibration) |
| 引脚 38 | RESET — Hard reset (active low) |
| 引脚 39 | GND — Analog ground |
| 引脚 40 | VD2 — Digital core / driver supply rail |
| 引脚 41 | DGND — Digital ground |
| 引脚 42 | DRVDD — Digital output driver supply |
| 引脚 43 | OA1- — Offset adjustment / spare pin per datasheet |
| 引脚 44 | OA2- — Offset adjustment / spare pin per datasheet |
| 引脚 45 | A1_BIAS — Channel 1 bias / decouple pin |
| 引脚 46 | A2_BIAS — Channel 2 bias / decouple pin |
| 引脚 47 | VA3 — Analog supply |
| 引脚 48 | GND — Analog ground |
| 引脚 49 | VA4 — Analog supply |
| 引脚 50 | VA5 — Analog supply |
| 引脚 51 | GND — Analog ground |
| 引脚 52 | AGND_SENSE — Analog ground-sense pin per datasheet |
| 引脚 53 | TEST — Test mode pin (tie low in normal operation) |
| 引脚 54 | INEXT+ — Reference positive input (used with external reference) |
| 引脚 55 | INEXT- — Reference negative input (used with external reference) |
| 引脚 56 | VSENSE — Reference sense pin per datasheet |
| 引脚 57 | VA6 — Analog supply |
| 引脚 58 | VA7 — Analog supply |
| 引脚 59 | VA8 — Analog supply |
| 引脚 60 | VA9 — Analog supply |
| 引脚 61 | GND — Analog ground |
| 引脚 62 | VA10 — Analog supply |
| 引脚 63 | VA11 — Analog supply |
| 引脚 64 | VA12 — Analog supply |
典型应用
ADC12D040CIVSX/NOPB 适用于 7 应用s: Digital Oscilloscope / Waveform Digitizer Front End, Communications Receiver IF Sampling, Medical Imaging Front End (Ultrasound / MRI Pre-ADC), CCD / CIS Imaging Digitizer, Industrial Process Control Data Acquisition, Radar / Sonar Baseband Acquisition, Test & Measurement Instrumentation.
Digital Oscilloscope / Waveform Digitizer Front End
The ADC12D040CIVSX/NOPB's dual-channel simultaneous 40 MSPS sampling at 12-bit resolution and single +3.3V analog supply make it a strong fit for 100 MHz-class oscilloscope and waveform digitizer front ends. The pipelined architecture yields deterministic conversion latency, simplifying scope trigger placement, while the 600 mW dissipation per chip allows compact multi-channel digitizer designs without forced-air cooling. The two independent channels also support interleaved 80 MSPS acquisition when higher bandwidth is required. Place 0.1uF ceramic decoupling on each AVDD/DRVDD pin within 3 mm (per the ADC12D040 datasheet) and drive the analog inputs in true differential mode to maximize SFDR in dense multichannel layouts.
推荐
Communications Receiver IF Sampling
In IF-stage digitizers for communications receivers, the ADC12D040CIVSX/NOPB's dual 40 MSPS channels cleanly capture differential I/Q signals with matched timing and <=10 ps channel-to-channel skew. The DRVDD input accepts 1.8V to 3.3V, allowing direct connection to FPGA receiver banks without external level shifters in modern digital-IF designs. Internal sample-and-hold and selectable on-chip reference simplify BOM and layout. Per the ADC12D040 datasheet, the 600 mW dissipation supports sealed enclosure receiver designs; design tip - keep analog input traces length-matched within 0.5 mm to preserve the dual-channel gain/phase match.
推荐
Medical Imaging Front End (Ultrasound / MRI Pre-ADC)
The ADC12D040CIVSX/NOPB supports medical imaging front-end signal paths where 12-bit resolution and dual-channel matched acquisition are needed for low-noise beam-forming. The internal or external reference (selectable) enables single-temperature-coefficient calibration across channels for accurate array element weighting. -40 C to +85 C operation covers portable ultrasound carts. Per the TI ADC12D040 datasheet, the 600 mW dissipation allows fanless enclosure operation, which is essential in clinical environments; design tip - mount the reference bypass capacitor adjacent to the REFT/RB pins to minimize LF noise coupling.
推荐
CCD / CIS Imaging Digitizer
Imaging applications such as industrial line-scan cameras and document scanners benefit from the ADC12D040CIVSX/NOPB's dual-channel sample-and-hold which can digitize two CCD outputs simultaneously to support parallel readout paths. The 40 MSPS per channel comfortably handles standard CCD pixel rates (e.g., 30 MSPS at 12 bits) with timing headroom. Internal reference removes an external component, easing board space at the dense imaging-array end. Per TI datasheet, drive the analog inputs single-ended from the CCD's buffered output stage when running at moderate pixel rates to halve front-end complexity.
推荐
Industrial Process Control Data Acquisition
In multi-channel data-acquisition modules for industrial process control, the ADC12D040CIVSX/NOPB's two simultaneous channels and 12-bit resolution deliver sufficient dynamic range for transducer signal chains (pressure, flow, vibration). The single +3.3V supply simplifies integration with low-voltage industrial SBCs. Internal/external reference lets a calibration lab tune gain across channels using a single shared reference. Per the TI datasheet the device operates over -40 C to +85 C industrial temperature range; design tip - protect analog inputs with TVS clamps rated for 24V industrial transients because field wiring is often exposed to surges.
推荐
Radar / Sonar Baseband Acquisition
Phase-array radar and sonar baseband receivers use matched I/Q sampling to recover quadrature baseband content - the ADC12D040CIVSX/NOPB's simultaneous dual-channel acquisition with a shared clock input is exactly this requirement. The 12-bit resolution captures typical baseband SNR without saturating from strong returns, and the 600 mW dissipation suits fan-less sealed sonar arrays. Per the ADC12D040 datasheet, the dedicated analog/digital ground split into solid copper pours under the device substantially improves harmonic distortion performance at full-scale input.
推荐
Test & Measurement Instrumentation
Bench instruments such as signal analyzers and protocol analyzers leverage the ADC12D040CIVSX/NOPB's 12-bit 40 MSPS dual-channel capture for sub-25 MHz reference signals while keeping the bill of materials low. The 64-TQFP (10x10) package allows hand-soldering with moderate rework equipment - useful in low-volume test gear production. Per the TI datasheet, the selectable input range and sample-and-hold on each input enable direct connection to either single-ended probes or 50-ohm terminated differential probes.
推荐
推荐产品汇总
工程参考数据： ADC12D040CIVSX/NOPB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC12D040CIVS/NOPB | ADC12D065CIVSX/NOPB | ADC12D100CIVSX/NOPB | ADC12D040CIVSX | ADC12040CIVY |
|---|---|---|---|---|---|---|
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP - same package |
| Brand | Texas Instruments (ex National Semiconductor) | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Sampling Rate | 40 MSPS / channel | 40 MSPS / channel | 65 MSPS / channel (+62.5%) | 100 MSPS / channel (+150%) | 40 MSPS / channel | 40 MSPS (single channel) |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits (single channel) |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 |
| Analog Supply Voltage | 3.3 V (single) | 3.3 V (single) | 3.3 V (single) | 3.3 V (single) | 3.3 V (single) | 3.3 V (single) |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS / LVDS | Parallel LVDS | Parallel CMOS | Parallel CMOS |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Carrier / Packaging | Tape & Reel (TR) | Tray | Tape & Reel (TR) | Tape & Reel (TR) | Tape & Reel (TR), non-RoHS | Tray |
关键差异点
- Single +3.3V analog supply with split digital rail (2.4V-AVDD) （对比 ADC12D040CIVS/NOPB (tray variant))
- 40 MSPS per channel aggregate up to 80 MSPS in interleaved dual-channel （对比 ADC12D040CIVSX (non-RoHS))
- Pin-compatible with higher-speed siblings （对比 ADC12D065CIVSX/NOPB and ADC12D100CIVSX/NOPB)
- Dual-channel simultaneous sampling with deterministic pipeline latency （对比 Single-channel ADC12040CIVY)
设计说明
Place a 0.1 uF X7R (or better) ceramic decoupling capacitor within 3 mm of every AVDD and DRVDD pin, and a 10 uF bulk decoupling on each supply rail near the device. Per the TI ADC12D040 datasheet, split the ground plane into a continuous analog-only region under the analog inputs and reference, joined beneath the device ground pin to a digital-only region under the parallel output drivers. Avoid routing analog and digital traces across the ground-plane split; this prevents digital switching noise from coupling into the analog front-end and degrading SNR/SFDR at full-scale inputs.
Drive the analog inputs (AIN1+/AIN1-, AIN2+/AIN2-) in true differential mode whenever possible, even if the source is single-ended - using the inverting input as the return path preserves common-mode rejection of digital supply noise. Estimated: with AVDD = 3.3 V and VREF internal, the full-scale input is ~1.0 Vppd (peak-pedestal), so termination resistors must be scaled to that swing to maximize dynamic range. Also make sure the CAL pin sequence is observed after power-up; an uncalibrated converter ships with residual offset that visibly degrades SFDR until calibration completes.
Route CLK+ and CLK- as a 100-ohm differential pair with length matching to within 0.2 mm; skew between the differential clock edges directly converts into aperture-delay mismatch that shows as interleave spurs at the FFT output. Estimated: at 40 MSPS the clock period is 25 ns, so even 100 ps of differential skew shifts the effective sampling instant. Keep the clock reference source within the same supply noise environment as the ADC and place an RC pi-filter (e.g. 22 ohm / 100 pF) on the clock line close to the ADC to filter wideband supply noise.
At typical 600 mW dissipation in the 64-TQFP (10x10 mm) package, junction rise above ambient is modest - estimated 30-40 C with a 4-layer PCB and adequate ground-pour copper - which is well within the 125 C junction limit. For sealed enclosures with no airflow, however, ambient can climb; verify with a thermal probe in the worst case. If higher-power alternatives such as ADC12D100 are evaluated, derate against the smaller theta_JA profile of the same TQFP body before committing to a mechanical-only design.
合规信息
RoHS and REACH compliance per the /NOPB suffix in the TI ordering part number. Lead-free finish confirmed. AEC-Q100 status not applicable for this non-automotive ADC; halogen-free status not explicitly stated in the verified web data and is marked unknown.
