ADC12DL066CIVS - Dual 12-Bit 66-MSPS ADC, 450MHz BW | TI
料号： ADC12DL066CIVS ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.95 | $10,950.00 |
| 2,500 | $9.8 | $24,500.00 |
ADC12DL066CIVS 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog input and converts it to a discrete digital code, serving as the bridge between the analog physical world and digital signal processing. In the broader taxonomy, an ADC is a data converter, which sits within mixed-signal ICs, and ultimately within power management and signal-chain semiconductors. Pipeline ADCs like the ADC12DL066CIVS use multiple low-resolution stages to achieve high sample rates with low latency, suitable for communications and imaging.
Key features of this device include a typical differential non-linearity (DNL) of +/-0.5 LSB, signal-to-noise ratio (SNR) of 66 dB at fIN = 10 MHz, and spurious-free dynamic range (SFDR) of similar magnitude at the same input frequency. The pipeline architecture delivers 2-channel simultaneous sampling at 66 MSPS, and the 450 MHz input bandwidth allows the ADC to handle IF-sampling in communications receivers as well as video and imaging front-ends.
Internally, the ADC12DL066CIVS uses a pipelined switched-capacitor core with proprietary calibration to maintain linearity and low spurious content across the rated temperature range. The internal reference and built-in sample-and-hold reduce external component count, while power-down mode enables low standby current in battery-powered or duty-cycled systems.
Typical applications include IF sampling in software-defined radios, medical ultrasound receive paths, image sensor digitizers, multi-channel data acquisition systems, and industrial instrumentation. It is a drop-in pin-compatible successor to the ADC12D040 within the same 64-TQFP footprint for upgrades seeking higher throughput.
Designers should provide a clean low-noise analog supply, good input driving amplifier (often a fully-differential amplifier), and proper PCB layout to avoid coupling digital switching noise into the analog front-end. Decoupling capacitors must be placed close to the supply and reference pins.
This page synthesizes distributor pricing, drop-in alternatives, and practical PCB and layout design notes not found in the bare manufacturer datasheet, with comparison tables and trade-off analyses tailored for engineers evaluating mid-speed dual ADCs.
直接替换替代料： ADC12DL066CIVS ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC12DL066CIVS （相同外形与封装尺寸） ——差异在于 Differential Non-Linearity (DNL), Number of Channels, Operating Temperature Range, Package, Power Down Mode.
快速对比工具——选择替代料号进行并排对比：
ADC12DL066CIVS/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12DL065CIVS/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12040CIVY
✅ 直接替换✓ 有现货
$5.52 / 个
查看数据手册 →ADC12DL066CIVS 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate (per channel) | 66 MSPS |
| Input Bandwidth | 450 MHz |
| Architecture | Pipelined |
| Supply Voltage (Analog) | 3.3 V (single supply) |
| Digital I/O Supply | 2.4 V to 3.3 V |
| Differential Non-Linearity (DNL) | +/-0.5 LSB (typ) |
| Signal-to-Noise Ratio (SNR, fIN=10 MHz) | 66 dB (typ) |
| Reference | Internal (with external option) |
| Output Format | Choice of Binary or 2's Complement |
| 工作温度范围 | -40C to +85C |
| 封装 | 64-TQFP (PAG) 10x10 mm |
| Pin Compatibility | Drop-in compatible with ADC12D040 |
| Power Down Mode | Yes |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (NOPB suffix) |
ADC12DL066CIVS 引脚配置
| 引脚 1 | VD — Digital supply voltage (2.4V to 3.3V) |
| 引脚 2 | DGND — Digital ground |
| 引脚 3 | D0A — Channel A data output bit 0 (LSB) |
| 引脚 4 | D1A — Channel A data output bit 1 |
| 引脚 5 | D2A — Channel A data output bit 2 |
| 引脚 6 | D3A — Channel A data output bit 3 |
| 引脚 7 | D4A — Channel A data output bit 4 |
| 引脚 8 | D5A — Channel A data output bit 5 |
| 引脚 9 | D6A — Channel A data output bit 6 |
| 引脚 10 | D7A — Channel A data output bit 7 |
| 引脚 11 | D8A — Channel A data output bit 8 |
| 引脚 12 | D9A — Channel A data output bit 9 |
| 引脚 13 | D10A — Channel A data output bit 10 |
| 引脚 14 | D11A — Channel A data output bit 11 (MSB) |
| 引脚 15 | DRVDD — Digital output driver supply |
| 引脚 16 | DR_GND — Digital output driver ground |
| 引脚 17 | D0B — Channel B data output bit 0 (LSB) |
| 引脚 18 | D1B — Channel B data output bit 1 |
| 引脚 19 | D2B — Channel B data output bit 2 |
| 引脚 20 | D3B — Channel B data output bit 3 |
| 引脚 21 | D4B — Channel B data output bit 4 |
| 引脚 22 | D5B — Channel B data output bit 5 |
| 引脚 23 | D6B — Channel B data output bit 6 |
| 引脚 24 | D7B — Channel B data output bit 7 |
| 引脚 25 | D8B — Channel B data output bit 8 |
| 引脚 26 | D9B — Channel B data output bit 9 |
| 引脚 27 | D10B — Channel B data output bit 10 |
| 引脚 28 | D11B — Channel B data output bit 11 (MSB) |
| 引脚 29 | DR_GND — Digital output driver ground |
| 引脚 30 | PD — Power-down input (active high) |
| 引脚 31 | FSR/PD — Full-scale range / power-down mode select |
| 引脚 32 | CLK — Clock input |
| 引脚 33 | DGND — Digital ground |
| 引脚 34 | VD — Digital supply voltage |
| 引脚 35 | DGND — Digital ground |
| 引脚 36 | AIN — Channel A analog input (positive) |
| 引脚 37 | AINB — Channel A analog input (negative) |
| 引脚 38 | REFT — Top reference voltage (decoupling) |
| 引脚 39 | VA — Analog supply voltage (3.3V) |
| 引脚 40 | AGND — Analog ground |
| 引脚 41 | VREF — Reference voltage output/input |
| 引脚 42 | REFB — Bottom reference voltage (decoupling) |
| 引脚 43 | AGND — Analog ground |
| 引脚 44 | VA — Analog supply voltage (3.3V) |
| 引脚 45 | BIN — Channel B analog input (positive) |
| 引脚 46 | BINB — Channel B analog input (negative) |
| 引脚 47 | AGND — Analog ground |
| 引脚 48 | VA — Analog supply voltage (3.3V) |
| 引脚 49 | AGND — Analog ground |
| 引脚 50 | VA — Analog supply voltage (3.3V) |
| 引脚 51 | AGND — Analog ground |
| 引脚 52 | VA — Analog supply voltage (3.3V) |
| 引脚 53 | AGND — Analog ground |
| 引脚 54 | VA — Analog supply voltage (3.3V) |
| 引脚 55 | AGND — Analog ground |
| 引脚 56 | VA — Analog supply voltage (3.3V) |
| 引脚 57 | REFT — Top reference voltage (decoupling) |
| 引脚 58 | VREF — Reference voltage output/input |
| 引脚 59 | REFB — Bottom reference voltage (decoupling) |
| 引脚 60 | AGND — Analog ground |
| 引脚 61 | BINB — Channel B analog input (negative) |
| 引脚 62 | BIN — Channel B analog input (positive) |
| 引脚 63 | VA — Analog supply voltage (3.3V) |
| 引脚 64 | AGND — Analog ground |
典型应用
ADC12DL066CIVS 适用于 6 应用s: Software-Defined Radio (IF Sampling), Medical Ultrasound Receive Path, Multi-Channel Data Acquisition, Image Sensor Digitizer, Communications Test Equipment, Industrial Instrumentation.
Software-Defined Radio (IF Sampling)
The ADC12DL066CIVS digitizes intermediate-frequency stages in software-defined radios where its 450 MHz analog input bandwidth and 66 MSPS per channel handle narrow-band IFs while still allowing generous anti-aliasing margin. Dual channels let a designer capture both I and Q streams simultaneously without skew, which is critical for demodulation accuracy. The 66 dB SNR keeps quantization noise below the receiver's thermal floor at typical IF power levels.
推荐
Medical Ultrasound Receive Path
Medical ultrasound imaging systems stack channels densely, so the ADC12DL066CIVS's dual-channel integration halves board area versus two single-channel ADCs while the 66 MSPS rate and 66 dB SNR support 20-30 MHz transducer bandwidth. Pipeline latency suits real-time beamforming, and the industrial -40C to +85C temperature range tolerates the warm chassis of cart-based scanners. Power-down mode lets unused channels idle between transmit pulses to manage thermal budget.
推荐
Multi-Channel Data Acquisition
Multi-channel data acquisition cards use the ADC12DL066CIVS's two simultaneous-sample channels to expand channel count without doubling cost; multiple ADC12DL066 chips can be clock-synchronized via the external reference and shared CLK for coherent sampling. The 12-bit resolution is adequate for vibration analysis, condition monitoring, and industrial instrumentation where 0.024% full-scale step size is sufficient. Digital I/O from 2.4 V to 3.3 V simplifies connection to modern low-voltage FPGAs.
推荐
Image Sensor Digitizer
Line-scan and area-scan camera front-ends use the ADC12DL066CIVS to convert analog pixel streams into 12-bit digital words at up to 66 MSPS per channel; its 450 MHz input bandwidth preserves fast transient edge information from CMOS or CCD sensors without smearing. Dual-channel simultaneous sampling lets one ADC handle two sensor tap points in lock-step, simplifying calibration. The 64-TQFP package also provides adequate thermal margin for industrial vision environments with elevated ambient temperatures.
推荐
Communications Test Equipment
Communications test and measurement instruments - signal analyzers, vector signal generators, protocol testers - depend on the ADC12DL066CIVS for accurate digitization of modulated waveforms. The 12-bit resolution and 66 dB SNR give enough dynamic range to resolve constellation points in 64-QAM and similar dense schemes, while 450 MHz input bandwidth allows direct sampling of intermediate bands. The internal reference simplifies calibration routines in test racks.
推荐
Industrial Instrumentation
Process-control and instrumentation front-ends use the ADC12DL066CIVS for digitizing transducer outputs including strain gauges, accelerometers, and analog sensor conditioning chains. The pipeline architecture's deterministic latency allows tight synchronization with control loops. The industrial -40C to +85C operating range covers factory-floor conditions, and the single +3.3 V analog supply simplifies power-tree design alongside low-voltage digital rails typical in PLC modules.
推荐
推荐产品汇总
工程参考数据： ADC12DL066CIVS ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC12DL066CIVS/NOPB | ADC12DL065CIVS/NOPB | ADC12040CIVY |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-TQFP (PAG) 10x10 mm | 64-TQFP (PAG) 10x10 mm | 64-TQFP (PAG) 10x10 mm | 64-TQFP family |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 |
| Sample Rate (per channel) | 66 MSPS | 66 MSPS | 65 MSPS | 40 MSPS |
| Supply Voltage | 3.3 V (single) | 3.3 V (single) | 3.3 V (single) | 3.3 V (single) |
| RoHS Compliance | Compliant (NOPB suffix) | RoHS Compliant | RoHS Compliant | RoHS Compliant |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
关键差异点
- Higher sample rate (66 MSPS vs 65 MSPS) for additional throughput margin （对比 ADC12DL065CIVS/NOPB)
- Dual-channel simultaneous sampling in 64-TQFP, single-channel competitor needs two parts （对比 ADC12040CIVY)
- Wide 450 MHz analog input bandwidth enables IF-sampling （对比 Narrower-band ADC competitors)
设计说明
Use a dedicated analog ground plane split from the digital ground, joined at a single point near the ADC's AGND pins. Keep the analog input traces short and matched in length, and place the input driving amplifier within 1 inch of the AIN/AINB pins to minimize common-mode noise pickup. Place 0.1 uF ceramic bypass capacitors as close as possible to every VA pin and a single 10 uF tantalum or ceramic bulk capacitor near the supply entry.
Route the CLK signal with controlled 50-ohm impedance and keep it away from analog input traces to avoid coupling. If using a differential clock source, route CLK and its complement with length matching within 100 mils. Place a clock buffer (such as a TI CDCLVC1310 or similar) close to the ADC to avoid reflections on long clock traces.
The ADC12DL066CIVS benefits from a low-noise LDO regulator such as the TI TPS7A47 or TPS7A30 to provide the clean +3.3 V analog VA supply required for best SFDR. Avoid sourcing VA from a switching regulator directly; if unavoidable, add a ferrite bead and bulk filtering. Keep the digital VD and DRVDD supplies isolated from VA with separate ground return paths.
Do not leave the REFT, REFB, and VREF pins floating - each requires a decoupling capacitor per the datasheet reference circuit (typically 0.1 uF plus 10 uF). Failure to bypass reference pins causes degraded SNR and excessive harmonic distortion. Ensure the PD pin is held low during normal operation or the ADC will enter power-down mode unexpectedly.
合规信息
ADC12DL066CIVS (without NOPB suffix) may not be fully RoHS-compliant; use ADC12DL066CIVS/NOPB for full RoHS/lead-free compliance. AEC-Q100 is not applicable - this is a commercial/industrial-grade part operating from -40C to +85C.
