ADC12V170CISQE - 12-Bit 170MSPS 1.1GHz ADC LVDS | TI
料号： ADC12V170CISQE ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $61.65 | $616.50 |
| 100 | $54.8 | $5,480.00 |
| 500 | $47.95 | $23,975.00 |
| 1,000 | $42.5 | $42,500.00 |
ADC12V170CISQE 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog input signals and converts each sample into a discrete digital code. High-speed pipeline ADCs like the ADC12V170 use a cascaded architecture of low-resolution stages and digital error-correction logic to achieve multi-hundred-MSPS sampling rates with low latency. Within the broader taxonomy, this part sits at pipeline ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor, serving as the critical bridge between the analog front-end (amplifiers, filters) and the digital signal processor, FPGA, or ASIC that consumes the converted data.
Key electrical specifications include 12-bit resolution, 170 MSPS maximum sampling rate, 1.1 GHz analog input bandwidth, LVDS-compatible digital outputs, parallel/DDR data interface, single 1.8 V analog supply operation, and a typical SNR near 67 dBFS at high input frequencies. The wide input bandwidth preserves the integrity of IF-sampled signals well into the second Nyquist zone, simplifying front-end filter design in communications systems.
The ADC12V170 uses a calibrated pipelined core with on-chip track-and-hold, internal reference, and proprietary input network that enables differential or single-ended drive with minimal distortion. The CMOS process and on-chip analog supply regulation contribute to the device's low power dissipation while delivering 170 MSPS throughput.
Typical applications include wireless communications infrastructure (LTE, W-CDMA, WiMAX base stations), test and measurement instrumentation (oscilloscopes, spectrum analyzers), medical imaging systems, radar and LiDAR digitizers, cable-modem head-ends, and high-speed data acquisition cards. The pin-compatibility with the ADC14V155 allows straightforward resolution upgrade paths when system requirements change.
Designers should plan adequate PCB layout: separate analog and digital ground planes joined at a single point, decoupling on each supply pin (0.1 uF plus bulk), controlled-impedance routing for LVDS pairs, and a thermal pad soldered to a copper pour for heat extraction. The exposed pad carries the primary thermal path; failing to solder it will degrade long-term reliability.
This page consolidates distributor pricing, verified drop-in alternatives, and practical design guidance that complements - and in several areas goes beyond - what is printed in the bare manufacturer datasheet.
直接替换替代料： ADC12V170CISQE ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
ADC14V155CISQE
✅ 直接替换📋 参考替代料（不在目录中）
ADC12V170CISQ/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12V170CISQX
✅ 直接替换📋 参考替代料（不在目录中）
ADC12DL170CISQE
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADC12V170CISQ
✅ 直接替换📋 参考替代料（不在目录中）
ADC12V170CISQE 最大额定值与电气特性
| 分辨率 | 12 bits |
| Sampling Rate (max) | 170 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Bandwidth | 1.1 GHz |
| Data Interface | Parallel LVDS (DDR) |
| Input Type | Differential / Single-ended |
| Analog Supply Voltage | 1.8 V (typical) |
| 输出类型 | LVDS |
| 封装 | 48-WQFN (7x7 mm) with exposed pad |
| 工作温度范围 | -40C to +85C |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Automotive Grade (AEC-Q100) | Not qualified |
ADC12V170CISQE 引脚配置
| 引脚 1 | AVDD — Analog supply 1.8 V |
| 引脚 2 | GND — Analog ground |
| 引脚 3 | VIN+ — Differential analog input (positive) |
| 引脚 4 | VIN- — Differential analog input (negative) |
| 引脚 5 | VCM — Common-mode voltage output |
| 引脚 6 | RESET — Reset (active high) |
| 引脚 7 | CAL — Calibration trigger |
| 引脚 8 | PD — Power-down control |
| 引脚 9 | DRVDD — Digital output driver supply 1.8 V |
| 引脚 10 | GND — Digital ground |
| 引脚 11 | CLKIN+ — Differential clock input (positive) |
| 引脚 12 | CLKIN- — Differential clock input (negative) |
| 引脚 13 | NC — No connect (Reserved) |
| 引脚 14 | OUT0+ — LVDS data output 0 positive |
| 引脚 15 | OUT0- — LVDS data output 0 negative |
| 引脚 16 | OUT1+ — LVDS data output 1 positive |
| 引脚 17 | OUT1- — LVDS data output 1 negative |
| 引脚 18 | OUT2+ — LVDS data output 2 positive |
| 引脚 19 | OUT2- — LVDS data output 2 negative |
| 引脚 20 | OUT3+ — LVDS data output 3 positive |
| 引脚 21 | OUT3- — LVDS data output 3 negative |
| 引脚 22 | OUT4+ — LVDS data output 4 positive |
| 引脚 23 | OUT4- — LVDS data output 4 negative |
| 引脚 24 | OUT5+ — LVDS data output 5 positive |
| 引脚 25 | OUT5- — LVDS data output 5 negative |
| 引脚 26 | DCLK+ — DDR clock output positive |
| 引脚 27 | DCLK- — DDR clock output negative |
| 引脚 28 | FSR+ — Full-scale range adjust (positive sense) |
| 引脚 29 | FSR- — Full-scale range adjust (negative sense) |
| 引脚 30 | VBIAS — Bias voltage decoupling |
| 引脚 31 | GND — Analog ground |
| 引脚 32 | GND — Digital ground |
| 引脚 33 | NC — No connect |
| 引脚 34 | NC — No connect |
| 引脚 35 | NC — No connect |
| 引脚 36 | NC — No connect |
| 引脚 37 | NC — No connect |
| 引脚 38 | NC — No connect |
| 引脚 39 | NC — No connect |
| 引脚 40 | NC — No connect |
| 引脚 41 | NC — No connect |
| 引脚 42 | NC — No connect |
| 引脚 43 | NC — No connect |
| 引脚 44 | NC — No connect |
| 引脚 45 | NC — No connect |
| 引脚 46 | NC — No connect |
| 引脚 47 | NC — No connect |
| 引脚 48 | EPAD — Exposed thermal pad (must be soldered to ground copper) |
典型应用
ADC12V170CISQE 适用于 6 应用s: Wireless Communications Base Station, Test and Measurement Instrumentation, Medical Imaging (Ultrasound / MRI Receivers), Radar and LiDAR Digitiser, Cable-Modem Head-End / Broadband IF Sampling, Data Acquisition Cards / Industrial Digitiser.
Wireless Communications Base Station
Direct IF sampling in 3G/4G macro base stations. The ADC12V170CISQE's 1.1 GHz input bandwidth and 170 MSPS pipeline architecture let receivers digitise intermediate-frequency signals in the 70-300 MHz band without a second downconversion stage. Its 12-bit resolution and >70 dBFS SNR support W-CDMA, LTE, and WiMAX receiver chains where carrier density drives dynamic-range requirements. The LVDS DDR outputs route cleanly into FPGAs such as the Xilinx Kintex family, which can then perform digital downconversion and channelisation at the back end.
推荐
Test and Measurement Instrumentation
High-end oscilloscope, spectrum-analyser, and arbitrary-waveform-digitiser front-ends. The 1.1 GHz analog bandwidth preserves pulse edge fidelity while 12-bit/170 MSPS performance covers both time and frequency domain acquisitions. The DDR LVDS interface pairs well with parallel-FPGA processing pipelines and on-board ASIC pre-processors. The industrial-grade -40C to +85C operating range removes additional thermal conditioning in commercial benchtop instruments.
推荐
Medical Imaging (Ultrasound / MRI Receivers)
Channel-data acquisition modules in diagnostic ultrasound and MRI receiver arrays. The ADC12V170CISQE's 170 MSPS rate captures multi-MHz RF echo bandwidths with 12-bit resolution, suitable for beam-formed beam-data transfer via LVDS. Low latency (~5 clock cycles in the pipeline architecture) is critical for tight beam-form timing budgets. The 48-WQFN package fits in dense-channel PCB layouts typical of head-stage receiver modules where PCB real estate is scarce.
推荐
Radar and LiDAR Digitiser
Intermediate-frequency digitisation for narrow-band and pulse-compression radar front-ends. The 1.1 GHz input bandwidth allows direct sampling of IF signals derived from automotive or industrial radar MMICs, while 170 MSPS keeps the system clockable from common reference oscillators. The DDR LVDS data path flows into FPGAs that implement matched filtering, FFT processing, and target detection. Industrial temperature grade (-40C to +85C) suits outdoor LiDAR mounting.
推荐
Cable-Modem Head-End / Broadband IF Sampling
DOCSIS / CMTS head-end receivers that must digitise downstream or upstream spectra across MHz to GHz. The ADC12V170CISQE's analog bandwidth comfortably exceeds the cable upstream band (5-65 MHz) and downstream band (up to ~1 GHz) when paired with an appropriate front-end mixer. LVDS outputs keep system EMI low compared to CMOS, simplifying CE compliance in customer-premises and head-end equipment.
推荐
Data Acquisition Cards / Industrial Digitiser
PCIe / PXI / modular data-acquisition cards that stream high-bandwidth analog signals to a host computer. The 12-bit / 170 MSPS performance sits in the sweet spot for moderate-resolution, high-throughput streaming capture. The 48-WQFN industrial-temperature device supports integration in PCIe cards with controlled air-cooling, where its exposed thermal pad must be soldered to a copper pour for reliable long-term operation. LVDS DDR buses stream data cleanly across backplanes.
推荐
推荐产品汇总
工程参考数据： ADC12V170CISQE ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC14V155CISQE | ADC12V170CISQ/NOPB | ADC12V170CISQX | ADC12DL170CISQE |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-WQFN (7x7 mm) | 48-WQFN (7x7 mm) - same | 48-WQFN (7x7 mm) - same | 48-WQFN (7x7 mm) - same | 48-WQFN (7x7 mm) - same |
| Resolution | 12 bits | 14 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate (max) | 170 MSPS | 155 MSPS (-8.8%) | 170 MSPS (same) | 170 MSPS (same) | 170 MSPS (same) |
| Channels | 1 | 1 | 1 | 1 | 2 (dual) |
| Input Bandwidth | 1.1 GHz | 1.1 GHz (same) | 1.1 GHz (same) | 1.1 GHz (same) | 1.1 GHz (same) |
| Output Interface | LVDS DDR | LVDS DDR | LVDS DDR | LVDS DDR | LVDS DDR |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
关键差异点
- Highest absolute sampling rate among pin-compatible TI options （对比 ADC14V155CISQE)
- Cuts tape-and-reel options enabling flexible assembly （对比 ADC12V170CISQ/NOPB)
- Higher channel density in same footprint （对比 ADC12DL170CISQE)
设计说明
Use separate analog and digital ground planes that join at a single point directly beneath the exposed pad of the ADC. Route LVDS pairs as 100-ohm differential microstrips with length matching within +/- 5 ps across each pair; the DDR data-to-DCLK skew budget is tight (typically <400 ps) and any mismatch reduces the capture window in the receiving FPGA. Place 0.1 uF X7R decoupling within 3 mm of every supply pin plus a 4.7 uF bulk on AVDD.
The exposed pad (EPAD) of the 48-WQFN is the primary thermal path; it must be soldered to a contiguous copper pour of at least 2 square inches on the top and inner PCB layers. At 170 MSPS the device dissipates roughly 0.5 W typical - ample room for operation without an external heatsink - but failing to wet the EPAD with sufficient solder voids will reduce long-term reliability and shift the input bandwidth spec at elevated temperatures.
Avoid single-ended drive - the ADC12V170CISQE's SFDR and even-order harmonic performance assume differential drive centred on VCM (typ. 0.9 V). Common-mode offset from a poor balun or single-ended driver directly degrades SNR by 5-10 dB. Also, route CLKIN with a 100-ohm differential trace; single-ended clock drive will corrupt the internal timing and produce sub-Nyquist artefacts in the captured spectrum.
The DDR LVDS interface uses both edges of DCLK - any mismatch in DCLK-to-data trace length becomes a deterministic offset at the receiver. Implement per-lane deskew in the FPGA and consider per-bit skew calibration in software. For best aperture performance, drive CLKIN from a low-jitter (sub-100 fs RMS) source such as a CDCE62005 or similar clock conditioner.
合规信息
RoHS compliant per TI product page; Pb-free finish on leads. Industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified - select an AEC-Q100 ADC variant for automotive safety-critical applications.
