ADS2806Y/1K5G4 - 12-Bit 32-MSPS Dual ADC | Texas Instruments
料号： ADS2806Y/1K5G4 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $35.5 | $35.50 |
| 10 | $31.95 | $319.50 |
| 100 | $28.4 | $2,840.00 |
| 500 | $25.1 | $12,550.00 |
| 1,000 | $22.3 | $22,300.00 |
ADS2806Y/1K5G4 概述
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog input signals into discrete digital output codes, forming the bridge between real-world analog transducers and digital signal processing. Pipelined ADCs use a multi-stage architecture to achieve high sampling rates while maintaining resolution, making them the dominant topology for communications, radar, and instrumentation IF sampling where tens of megasamples per second are required. The ADS2806 specifically targets dual-channel IF processing in basestations and test equipment.
Key features include flexible input range of 2 Vp-p to 3 Vp-p, low DLE of ±0.4 LSB, internal 2.5 V reference with option for external reference, and an LVCMOS-compatible digital interface. The high-bandwidth track-and-hold enables excellent spurious performance beyond the Nyquist rate. Power-down modes reduce consumption to microampere levels for portable applications. The HTQFP-64 power package with exposed pad provides robust thermal performance for sustained high-speed operation.
The ADS2806 uses a switched-capacitor pipelined architecture with seven internal 1.5-bit stages plus a final 2-bit flash, producing 12-bit codes at up to 32 MSPS on each channel. The dual channels can be sampled simultaneously, enabling I/Q digital downconversion in communications receivers. The high SFDR of 73 dB at fIN = 10 MHz preserves spurious-free dynamic range critical for multi-carrier basestation IF chains.
Typical applications include communications IF processing, communications basestation receivers, test and measurement equipment, radar and lidar digitizers, and dual-channel instrumentation digitizers. Dual simultaneous sampling is essential for orthogonal I/Q acquisition in software-defined radio.
When designing with this ADC, maintain a low-noise, low-impedance analog input path with proper 50-ohm or differential driving termination. The exposed thermal pad MUST be soldered to a sufficiently large ground plane to dissipate switching charge currents at 32 MSPS. Bypass AVDD and DRVDD with 0.1 uF ceramic capacitors placed within 5 mm of each supply pin.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving procurement engineers and hardware designers a one-stop sourcing and evaluation resource.
直接替换替代料： ADS2806Y/1K5G4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADS2806Y/1K5G4 （相同外形与封装尺寸） ——差异在于 Data Interface, Input Range, Operating Temperature, Part Number, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
ADS2806Y/1K5
✅ 直接替换📋 参考替代料（不在目录中）
ADS2807Y/1K5G4
✅ 直接替换✓ 有现货
$20.5 / 个
查看数据手册 →ADS2807Y/1K5
✅ 直接替换📋 参考替代料（不在目录中）
ADS2806Y/1K5G4 最大额定值与电气特性
| Manufacturer | Texas Instruments |
| Part Number | ADS2806Y/1K5G4 |
| 分辨率 | 12 bits |
| Number of Channels | 2 (dual) |
| Sampling Rate (Per Second) | 32 MSPS |
| Data Interface | Parallel (LVCMOS) |
| Architecture | Pipelined |
| Input Range | 2 Vp-p to 3 Vp-p (flexible) |
| Spurious-Free Dynamic Range (SFDR) | 73 dB at fIN = 10 MHz |
| SNR (2 Vp-p input) | 67 dB |
| SNR (3 Vp-p input) | 69 dB |
| Differential Linearity Error (DLE) | ±0.4 LSB |
| Reference | Internal or External |
| 电源电压 | 5 V (analog) / 3.3 V or 5 V (digital) |
| 工作温度 | -40C to +85C |
| 封装 | HTQFP-64 (PowerPAD, 10x10 mm) |
| 安装类型 | Surface Mount |
| Packaging Type | Tape and Reel (TR) |
| RoHS 状态 | Compliant (lead-frame RoHS-compatible) |
ADS2806Y/1K5G4 htqfp-64 (powerpad, 10x10 mm) 引脚配置指南
ADS2806Y/1K5G4（htqfp-64 (powerpad, 10x10 mm) 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： ADS2806Y/1K5G4.
请参阅 数据手册 以查看完整引脚配置。
典型应用
ADS2806Y/1K5G4 适用于 6 应用s: Communications Basestation IF Sampling, Test and Measurement Instrumentation, Radar and Lidar Signal Digitization, Software-Defined Radio (SDR) Receivers, Medical Imaging Ultrasound Front-End, Industrial Process Control and Data Acquisition.
Communications Basestation IF Sampling
The ADS2806Y/1K5G4 is engineered for cellular basestation IF chains where 12-bit resolution at 32 MSPS meets GSM, UMTS, and LTE receiver requirements. Its 73 dB SFDR at 10 MHz input suppresses intermodulation distortion in multi-carrier power amplifiers, allowing accurate demodulation of closely spaced carriers in a 20 MHz LTE signal without adjacent-channel leakage. The dual-channel simultaneous sampling provides I/Q acquisition for direct-conversion and superheterodyne receivers, replacing two discrete ADCs with a single IC. Place the ADS2806 between the IF SAW filter output and the FPGA/CPU DSP front-end; ensure the analog input trace is 50-ohm impedance-controlled differential pair with length matching within 0.5 mm. According to the TI ADS2806 datasheet, the part's 67 dB SNR at 2 Vp-p satisfies basestation receiver sensitivity requirements while the 32 MSPS sampling rate provides 2x oversampling headroom for digital filtering. This saves PCB area compared to dual-ADC designs and reduces system BOM cost by integrating two converters into one TQFP-64 footprint.
推荐
Test and Measurement Instrumentation
In digital oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers, the ADS2806Y/1K5G4 captures transient analog signals with 12-bit resolution at 32 MSPS for both channels simultaneously. The 73 dB SFDR preserves harmonic structure of measured waveforms, allowing engineers to quantify subtle distortion products down to -73 dBc - critical for audio amplifier characterization or power-supply ripple analysis. The dual-channel architecture captures two correlated signals (e.g., input vs. output of a DUT) in one acquisition, simplifying instrument front-end design. Per the TI datasheet, the flexible 2 Vp-p to 3 Vp-p input range accommodates probe attenuator outputs directly without additional gain stages. The HTQFP-64 package simplifies thermal design in instrument enclosures where multiple ADCs are stacked. Estimated application benefit: a 32 MSPS, 12-bit dual acquisition system with 67 dB SNR can digitize 100 kHz precision audio test signals with less than 0.01% measurement uncertainty, suitable for compliance test of audio components.
推荐
Radar and Lidar Signal Digitization
The ADS2806Y/1K5G4's 32 MSPS sampling enables digital radar baseband digitization for short-range automotive and industrial radar receivers at carrier frequencies up to 16 MHz (Nyquist). Its dual-channel architecture captures in-phase (I) and quadrature (Q) baseband signals simultaneously, preserving the phase relationship required for Doppler velocity extraction. Low differential linearity error of ±0.4 LSB prevents false-target generation in range-Doppler maps where spurious codes would otherwise appear as ghost returns. Per TI ADS2806 datasheet specifications, the flexible input range accommodates radar mixer outputs directly. The 67 dB SNR at 2 Vp-p input supports target SNR requirements for short-range radar down to -110 dBm echo levels after signal processing gain. Note: for automotive long-range radar at 76-81 GHz, an external demodulator and faster ADC such as TI ADC34J25IRGZ25 is required.
推荐
Software-Defined Radio (SDR) Receivers
In SDR platforms, the ADS2806Y/1K5G4 provides intermediate-frequency (IF) digitization for direct-sampling receivers operating in the HF to low-VHF range. The dual channels allow I/Q sampling of a quadrature demodulator output, eliminating the need for complex analog phasing networks. At 32 MSPS, the converter covers up to 16 MHz of instantaneous bandwidth, suitable for receiving wideband HF signals, AIS marine traffic, or wide-FM broadcast. Per the TI datasheet, the 73 dB SFDR at 10 MHz input ensures weak signals adjacent to strong carriers remain detectable - critical for amateur radio DXing and spectrum monitoring applications. The LVCMOS parallel interface simplifies hookup to Xilinx Spartan or Altera Cyclone FPGAs for real-time signal processing. Note that the TI parts pair well with the XC6SLX9 or similar low-cost FPGA, and A/D conversion at 32 MSPS places zero thermal stress on the FPGA's LVCMOS receiver pins, removing need for an external bus switch.
推荐
Medical Imaging Ultrasound Front-End
The ADS2806Y/1K5G4's dual-channel 12-bit 32 MSPS performance is well-suited for portable ultrasound imaging front-ends where multiple receive channels per transducer array must be digitized simultaneously. Each ADC samples I/Q beamformed baseband signals from transducer elements after analog beamforming, feeding digital beamforming FPGAs for image reconstruction. The 67 dB SNR provides adequate dynamic range for soft-tissue imaging, where 40 dB of tissue contrast is typical plus 20 dB detection headroom. Per TI datasheet, the low DLE of ±0.4 LSB preserves Doppler frequency accuracy essential for blood-flow velocity measurement in vascular ultrasound. The HTQFP-64 PowerPAD exposed thermal pad simplifies thermal management in dense multi-channel receive boards where 16+ ADCs may be placed. Note that for cart-based hospital ultrasound requiring higher channel counts and dynamic range, multi-channel ADCs like TI AFE5807 or AFE5808 are typically preferred.
推荐
Industrial Process Control and Data Acquisition
The ADS2806Y/1K5G4 provides dual-channel simultaneous sampling in industrial data acquisition systems (DAQs) where correlated sensor pairs must be measured at the same instant - for example, voltage and current in power metering, or strain and temperature on a load cell. Its 32 MSPS sample rate is far above the sensor bandwidth limits, allowing extensive oversampling averaging that improves effective resolution to 14-15 bits in low-bandwidth process signals (typically <100 kHz). Per TI ADS2806 datasheet, the flexible 2-3 Vp-p input range directly accommodates transducer outputs after signal conditioning. Industrial operating range of -40C to +85C supports deployment in outdoor panels and factory-floor enclosures. Estimated application: a 3-phase power meter digitizing voltage and current CT outputs benefits from simultaneous sampling for accurate real-power calculation, replacing two single-channel ADCs and reducing component count while maintaining IEC 62053-22 class 0.2 metrology accuracy.
推荐
推荐产品汇总
工程参考数据： ADS2806Y/1K5G4 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADS2806Y/1K5 | ADS2807Y/1K5G4 | ADS2807Y/1K5 |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-HTQFP (10x10) | 64-HTQFP (10x10) - same | 64-HTQFP (10x10) - same | 64-HTQFP (10x10) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Channels | 2 (dual) | 2 (dual) | 1 (single) | 1 (single) |
| Sampling Rate | 32 MSPS | 32 MSPS | 50 MSPS (+56%) | 50 MSPS (+56%) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS Compliant | Yes (G4 suffix lead-free) | Order-code dependent (G4 = compliant) | Yes (G4 suffix lead-free) | Order-code dependent (G4 = compliant) |
关键差异点
- Dual-channel simultaneous sampling at 32 MSPS per channel （对比 ADS2807Y/1K5G4)
- Lower cost at high quantity breaks than the ADS2807 family （对比 ADS2807Y/1K5G4)
- G4 suffix explicitly designates lead-free / RoHS-compliant finish （对比 ADS2806Y/1K5)
设计说明
The HTQFP-64 PowerPAD exposed thermal pad MUST be soldered to the PCB ground plane to dissipate heat generated at 32 MSPS sustained operation. Use a thermal via array (4-9 vias, 0.3 mm drill) under the pad to conduct heat to inner ground layers. Input traces should be 50-ohm impedance-matched differential pairs with length matching within 0.5 mm between the two signal halves, especially for input frequencies above 10 MHz where mismatched traces degrade SFDR.
Bypass AVDD and DRVDD supply pins with 0.1 uF ceramic capacitors placed within 5 mm of each pin, plus bulk 10 uF tantalum or polymer capacitors at the supply entry. The TI ADS2806 datasheet recommends separating analog and digital grounds with a single-point connection under the exposed thermal pad to prevent digital switching noise from coupling into analog inputs. Estimated: at 32 MSPS the typical AVDD current is approximately 90 mA per channel, so plan regulator capacity accordingly.
For input frequencies above 10 MHz, use a transformer-coupled differential input driver (such as Mini-Circuits ADT1-1WT or equivalent) rather than op-amp single-ended conversion. Transformer coupling provides the best SFDR performance and rejects common-mode noise. The clock input (CLK) must be clean with < 1 ps RMS jitter - phase noise on the clock directly degrades SNR by 6 dB per doubling of input frequency. Use a low-jitter clock generator such as TI CDCE925 for sensitive applications.
Do not exceed the absolute maximum AVDD voltage of 6 V or allow negative input voltages on AINP/AINM, as both will damage the ADC. The maximum sample rate of 32 MSPS should not be exceeded, even for short bursts. Ensure the input common-mode voltage is biased to AVDD/2 (typically 2.5 V) via the internal CM buffer or external resistors. The TQFP-64 package handling requires MSL 3 moisture-sensitive device compliance - bake at 125C for 24 hours if floor-life exposure exceeds the package's MSL limit.
合规信息
G4 suffix designates lead-free terminal finish per TI lead-frame RoHS transition announcement. Halogen-free status not explicitly confirmed in the provided source data. Not AEC-Q100 qualified - for automotive applications, an AEC-Q100-rated ADC such as TI ADC34J25 family should be selected.
