ADS6423IRGCR - Quad 12-Bit 80MSPS Serial LVDS ADC | TI
料号： ADS6423IRGCR ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.45 | $2,845.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $21.85 | $21,850.00 |
ADS6423IRGCR 概述
An ADC (analog-to-digital converter) is a semiconductor device that samples continuous analog input voltages and converts them into discrete digital codes. Pipelined ADCs use a cascade of low-resolution stages with inter-stage residue amplifiers to achieve high sampling rates while maintaining good linearity; the ADS6423 follows this architecture to deliver 80 MSPS across four independent channels. Within the broader power and signal chain, the ADC sits between analog front-ends (amplifiers, anti-alias filters) and an FPGA or ASIC that processes the digital data.
Key specifications include 12-bit resolution, 80 MSPS sampling rate, serialized LVDS digital interface, internal 3.5-dB coarse gain option for improved SFDR at high input frequencies, and a 3.3-V analog and digital supply. No external decoupling is required for the internal references, simplifying PCB layout. The 64-pin VQFN package integrates dense LVDS routing and provides a thermal pad for dissipation under multi-channel full-rate operation.
With 12-bit resolution and 80 MSPS sampling, the ADS6423IRGCR suits medical imaging front-ends, multi-channel communications receiver IF digitizers, radar signal acquisition, and industrial test instrumentation. Compared to dual-channel ADCs, the four-channel integration cuts board area, channel-to-channel skew, and per-channel cost. Compared to lower-speed SAR ADCs, the pipelined 80 MSPS architecture captures wideband modulated signals with minimal aperture jitter.
When designing with this part, route the LVDS pairs with controlled 100-ohm differential impedance, decouple AVDD and DVDD with 1 µF and 0.1 µF ceramics close to the pins, and tie the exposed thermal pad to a solid ground plane to keep junction temperature within the -40 °C to +85 °C operating range. Buffer or transform-couple analog inputs to keep common-mode voltage within the input common-mode range.
This page combines manufacturer datasheet specifications, distributor pricing tiers, and a same-family drop-in analysis to help engineers select pin-compatible ADCs for compact multi-channel systems at 80 MSPS.
直接替换替代料： ADS6423IRGCR ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADS6423IRGCR （相同外形与封装尺寸） ——差异在于 Package, Number of Channels, Resolution, Digital Supply Voltage, Input Type.
快速对比工具——选择替代料号进行并排对比：
ADS6424IRGCR
✅ 直接替换📋 参考替代料（不在目录中）
ADS6422IRGCR
✅ 直接替换📋 参考替代料（不在目录中）
ADS6423IRGCT
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADS6443IRGCR
✅ 直接替换✓ 有现货
$21.2 / 个
查看数据手册 →ADS6423IRGCRG4
✅ 直接替换📋 参考替代料（不在目录中）
ADS6423IRGCR 最大额定值与电气特性
| Manufacturer | Texas Instruments |
| Part Number | ADS6423IRGCR |
| 分辨率 | 12 bit |
| Number of Channels | 4 (Quad) |
| 采样率 | 80 MSPS |
| Architecture | Pipelined |
| Digital Interface | Serial LVDS (1-wire / 2-wire) |
| Number of Inputs | 4 differential |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 3.3 V |
| 封装 | 64-VQFN EP, 9 mm × 9 mm (RGC) |
| 安装类型 | Surface Mount |
| 工作温度范围 | -40 °C to +85 °C |
| Internal Reference | Yes (no external decoupling required) |
| Coarse Gain Option | 3.5 dB |
| RoHS 状态 | Compliant |
ADS6423IRGCR 引脚配置
| 引脚 1 | AVDD — Analog supply voltage (3.3 V) |
| 引脚 17 | AVSS — Analog ground |
| 引脚 33 | CLKIN — LVDS-compatible external clock input (sample rate) |
| 引脚 49 | DRVDD — Digital driver supply (3.3 V for LVDS) |
| 引脚 50 | DRVSS — Digital driver ground |
| 引脚 64 | PAD — Exposed thermal pad - tie to clean analog ground |
典型应用
ADS6423IRGCR 适用于 6 应用s: Medical Ultrasound Imaging Front-End, Multi-Channel Communications IF Receiver, Radar and Lidar Wideband Digitization, Industrial Test and Measurement Instrumentation, Multi-Channel Data Acquisition Card, Broadcast Video Production Switchers.
Medical Ultrasound Imaging Front-End
The ADS6423IRGCR fits medical ultrasound front-ends because its four simultaneously-sampled channels align with ultrasound transducer arrays that digitize multiple receive beams in parallel. At 12-bit resolution and 80 MSPS per channel, it captures returning echoes with sufficient dynamic range for tissue harmonic imaging, while serialized LVDS outputs compress four parallel buses into one to ease cable and connector pinout. The 64-pin VQFN package enables high channel density on small receiver boards where space is constrained near the transducer housing.
推荐
Multi-Channel Communications IF Receiver
In multi-carrier communications IF stages, the ADS6423IRGCR digitizes up to four intermediate-frequency channels at 80 MSPS, enabling parallel receivers for diversity or MIMO antennas. The pipelined 12-bit architecture maintains good SFDR at high IF frequencies, while internal reference and 3.5-dB coarse gain maximize linearity at the input. Its serialized LVDS interface pairs naturally with FPGA transceivers on baseband cards without adding bus-width to the backplane.
推荐
Radar and Lidar Wideband Digitization
The ADS6423IRGCR handles wideband radar and lidar digitization by delivering four channels of 80 MSPS, 12-bit data into serialized LVDS, a fit for phased-array radar beam-formers where multiple receive channels must be sampled simultaneously. The pipelined architecture preserves aperture timing across all four channels, which is critical for accurate beamforming angle-of-arrival estimation. Compact 9 mm × 9 mm QFN packaging permits dense placement close to the antenna front-end to minimize analog routing losses.
推荐
Industrial Test and Measurement Instrumentation
In industrial test equipment such as automated test stands or waveform recorders, the ADS6423IRGCR provides four 80 MSPS capture channels into a single 64-pin QFN footprint, reducing both per-channel cost and board area. Its DC-accurate 12-bit conversion handles transducer outputs from current shunts, strain gauges, and accelerometers in multi-axis test rigs. Serialized LVDS transfers data to a host FPGA over a small pin count, leaving room for additional channels on the same backplane.
推荐
Multi-Channel Data Acquisition Card
Multi-channel DAQ cards built around the ADS6423IRGCR leverage its quad-channel architecture to capture four analog inputs at 80 MSPS each from a single 64-pin QFN. Each channel feeds a serialized LVDS stream to a host FPGA or DSP, allowing modular PCIe or PXI-style digitizer cards to scale channel count by stacking additional ADC devices. The package's exposed thermal pad simplifies heat dissipation on densely populated DAQ boards.
推荐
Broadcast Video Production Switchers
Professional broadcast switchers using the ADS6423IRGCR benefit from four 80 MSPS, 12-bit channels per device to digitize multi-format video streams in a compact chassis. The serialized LVDS data delivery allows a single ADC to feed a downstream FPGA-based processing block over a minimal pin count, reducing board area and EMI. Internal reference and 3.3-V operation keep the power tree simple in space-constrained studio environments.
推荐
推荐产品汇总
工程参考数据： ADS6423IRGCR ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADS6424IRGCR | ADS6422IRGCR | ADS6423IRGCRG4 | ADS6443IRGCR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-VQFN (RGC) 9 mm × 9 mm | 64-VQFN (RGC) 9 mm × 9 mm - same | 64-VQFN (RGC) 9 mm × 9 mm - same | 64-VQFN (RGC) 9 mm × 9 mm - same | 64-VQFN (RGC) 9 mm × 9 mm - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit |
| Sampling Rate | 80 MSPS | 105 MSPS (+31%) | 65 MSPS (-19%) | 80 MSPS | 80 MSPS |
| Channels | 4 | 4 | 4 | 4 | 4 |
| Digital Interface | Serial LVDS (1-wire / 2-wire) | Serial LVDS (1-wire / 2-wire) | Serial LVDS (1-wire / 2-wire) | Serial LVDS (1-wire / 2-wire) | Serial LVDS (1-wire / 2-wire) |
| Analog Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Qty-1 Unit Price (approx.) | USD 38.50 | USD ~48.00 | USD ~32.00 | USD ~38.50 | USD ~55.00 |
关键差异点
- Pin-compatible across the ADS642X (12-bit) and ADS644X (14-bit) families （对比 ADS6422IRGCR)
- Faster sample rate than the 65 MSPS option in the same family （对比 ADS6422IRGCR)
- Lower cost than 14-bit family member at same sample rate （对比 ADS6443IRGCR)
设计说明
Route the four analog inputs with matched-length differential pairs, keeping the 100 Ω differential impedance controlled and physically short. Place a 1 µF and a 0.1 µF ceramic bypass close to each AVDD pin. The exposed thermal pad must be soldered to a clean analog ground pour with multiple vias, both to manage power dissipation and to provide a low-impedance return for the analog inputs.
Provide the 80 MHz LVDS-compatible clock to the CLKIN input through a transformer-coupled driver or low-jitter clock generator; sub-200 fs aperture jitter is essential to preserve SNR at 80 MSPS. Place series termination matching the 100 Ω differential impedance directly at the clock source to minimize reflections. Keep the clock trace well-isolated from noisy digital outputs.
Do not exceed the AVDD supply voltage of 3.3 V; the device is not tolerant to 5 V. The internal reference needs no external decoupling on the REFT/REFB pins - adding caps can cause startup issues. If the input common-mode voltage falls outside the rated range, distortion increases sharply; use a fully-differential ADC driver such as THS4521 to set the correct common-mode level.
合规信息
RGC suffix denotes TI's lead-free, RoHS-compliant packaging. AEC-Q100 qualification not stated in TI product page; use an automotive-grade TI ADC for vehicle applications.
