AM3357BZCZA80 - Sitara ARM Cortex-A8 800MHz MPU | TI
料号： AM3357BZCZA80 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $19.21 | $19.21 |
| 10 | $17.85 | $178.50 |
| 100 | $15.42 | $1,542.00 |
| 500 | $13.8 | $6,900.00 |
| 1,000 | $12.55 | $12,550.00 |
AM3357BZCZA80 概述
An ARM Cortex-A8 MPU is a system-on-chip class microprocessor that integrates CPU core, memory controller, graphics, and a wide peripheral set into one BGA. In the taxonomy of computing devices it sits below an application processor SoC and above a microcontroller: an MPU lacks internal flash (relies on external DDR/NOR/NAND) but offers full MMU, OS support (Linux, Android, RTOS), and rich connectivity peripherals (Ethernet, USB, CAN, PRU-ICSS). The AM335x family is widely used as a Linux-capable industrial MPU for HMI, PLC, and gateway products.
Key features of the AM3357 include a 32-bit ARM Cortex-A8 core with NEON, 200 MHz of MIPS-class performance headroom, two 32-bit DDR2/DDR3/DDR3L memory controllers with ECC, dual-port 1 Gbps Ethernet switch with IEEE 1588v2 support, two USB 2.0 high-speed ports (one OTG), and on-chip cryptography acceleration (AES, SHA, RNG). Graphics are handled by a programmable 24-bit LCD controller (up to 2048x2048) with touchscreen, and a separate 2D/3D graphics accelerator (SGX530) supports OpenGL ES 2.0.
Technical depth: the AM3357 implements the Programmable Real-time Unit Subsystem (PRU-ICSS) with dual 32-bit RISC cores operating at 200 MHz, deterministic I/O latency, and direct access to peripheral pins - enabling industrial protocols such as EtherCAT, Profibus, and PROFINET entirely in firmware. The device is manufactured in a 65 nm process and supports separate 1.8 V / 3.3 V supply rails with on-die LDO/power-management ICs.
Typical applications include industrial HMI panels, PLCs, motor drives, barcode scanners, portable data terminals, building automation gateways, and Linux-based IoT edge devices. The wide peripheral mix eliminates external companion chips for most designs.
When designing with the AM3357, ensure the PCB stack-up supports 0.8 mm BGA escape routing, provision an external DDR2/DDR3 memory with matched-length traces, and follow TI's Power-Sequencing recommendations for the dual-voltage supply.
This page synthesizes distributor pricing, drop-in cross-family alternatives, and PRU-ICSS design notes not found in the manufacturer datasheet.
直接替换替代料： AM3357BZCZA80 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
AM3358BZCZA80
✅ 直接替换📋 参考替代料（不在目录中）
AM3354BZCZA80
✅ 直接替换📋 参考替代料（不在目录中）
AM3356BZCZA80
✅ 直接替换📋 参考替代料（不在目录中）
AM3359BZCZA80
✅ 直接替换📋 参考替代料（不在目录中）
AM3352BZCZ80
✅ 直接替换📋 参考替代料（不在目录中）
AM3357BZCZA80 最大额定值与电气特性
| Core Architecture | ARM Cortex-A8 (32-bit) |
| Core Count | 1 |
| Maximum CPU Frequency | 800 MHz |
| Instruction Set | ARMv7-A with NEON SIMD and VFPv3 |
| Operating Voltage | 912 mV to 1.326 V (core) |
| I/O Voltage | 1.8 V / 3.3 V |
| 封装 | NFBGA-324 (15x15 mm, 0.8 mm pitch) |
| On-chip RAM | 64 KB SRAM |
| External Memory | DDR2 / DDR3 / DDR3L with ECC, NAND/NOR flash |
| Graphics Accelerator | SGX530 (OpenGL ES 2.0) |
| LCD Controller | 24-bit, up to 2048x2048 |
| Ethernet | 2x 10/100/1000 Mbps with IEEE 1588v2 |
| USB | 2x USB 2.0 HS (one OTG) |
| PRU-ICSS | 2x 32-bit PRU cores at 200 MHz |
| CAN | 2x CAN 2.0B |
| Cryptography | AES, SHA, RNG accelerator |
| 工作温度 | -40C to +105C |
| RoHS 状态 | Compliant |
AM3357BZCZA80 引脚配置
| 引脚 A1 | DDR_A0 — DDR address bit 0 (peripheral pin mux) |
| 引脚 B5 | VSS — Ground reference |
| 引脚 C12 | EMAC0_TXCLK — EMAC0 transmit clock (multiplexed) |
| 引脚 D15 | USB0_DP — USB0 data plus (multiplexed) |
| 引脚 F4 | VDD_CORE — Core supply 0.912-1.326 V |
| 引脚 G18 | SYSBOOT0 — Boot configuration bit 0 |
| 引脚 H8 | GPMC_AD0 — General Purpose Memory Controller address/data |
| 引脚 J16 | PRU0_ETH_MII0_TXD0 — PRU-ICSS MII transmit data 0 |
| 引脚 K2 | VDDS_DDR — DDR PHY supply 1.8 V |
| 引脚 L11 | I2C0_SDA — I2C0 serial data (multiplexed) |
| 引脚 M18 | MMC0_CLK — MMC0 clock (multiplexed) |
| 引脚 N3 | VDDS_PLL — PLL analog supply |
| 引脚 P9 | GPIO0_15 — General-purpose I/O |
| 引脚 R15 | SPI0_SCLK — SPI0 clock (multiplexed) |
| 引脚 T1 | NC — Not connected (per datasheet) |
| 引脚 U18 | UART0_TXD — UART0 transmit (multiplexed) |
| 引脚 W3 | RESETn — Global reset (active low) |
| 引脚 Y14 | PRU1_ETH_MII1_RXDV — PRU-ICSS1 MII receive data valid |
| 引脚 AA8 | CLKOUT — Clock output for external peripherals |
| 引脚 AB18 | LCD_DATA0 — LCD data bit 0 |
典型应用
AM3357BZCZA80 适用于 6 应用s: Industrial Human-Machine Interface (HMI) Panels, Programmable Logic Controller (PLC), Motor Drive and Servo Controller, Barcode Scanner / Portable Data Terminal, Industrial IoT Edge Gateway, Building Automation Controller.
Industrial Human-Machine Interface (HMI) Panels
The AM3357BZCZA80's 800 MHz ARM Cortex-A8 with integrated SGX530 3D graphics makes it a fit for industrial HMI panels driving 7-inch to 15-inch color TFT-LCDs at up to 2048x2048 resolution. Engineers typically pair the part with the TI TFP401A or SN65DSI83 DSI bridge and a 4-wire resistive touch controller. The SGX530 supports OpenGL ES 2.0, enabling Qt, Crank Storyboard, or LVGL graphics frameworks to render smooth animations while the Linux kernel handles input events and fieldbus communication. Per the AM335x TRM, the integrated LCD controller supports dual-overlays and color keying for menu systems without CPU load.
推荐
Programmable Logic Controller (PLC)
The AM3357BZCZA80 is widely used in PLC main processors where the PRU-ICSS dual 32-bit RISC cores implement EtherCAT, PROFINET IRT, or EtherNet/IP slave protocols entirely in firmware. Per TI's PRU-ICSS industrial SDK, deterministic cycle times under 1 microsecond are achievable, satisfying IEC 61131-3 real-time constraints. The Linux Cortex-A8 runs the IEC 61131-3 runtime (e.g., CODESYS, logi.CAD), EtherNet/IP scanner stack, and webserver HMI, while the PRUs offload deterministic bus cycles from the OS. The dual GbE ports with IEEE 1588v2 hardware timestamping enable daisy-chained linear topologies common in PLC backplanes.
推荐
Motor Drive and Servo Controller
In motor-drive and servo designs the AM3357BZCZA80 acts as the supervisory controller while the PRU-ICSS handles encoder sampling, PWM generation, and current-loop control. The PRU's single-cycle I/O access enables 50 kHz current-loop sampling without jitter, well-suited for FOC servo loops. The A8 core runs the trajectory planner, EtherCAT master stack, and the operator interface. The dual CAN ports support CANopen DS402 and CiA 402 motion profiles, while the integrated AES/SHA crypto accelerators secure fieldbus traffic. Per the TI Sitara motor-control reference design, this architecture replaces legacy DSP+MCU solutions.
推荐
Barcode Scanner / Portable Data Terminal
Portable barcode scanners and ruggedized data terminals leverage the AM3357BZCZA80's Cortex-A8 + Linux + USB 2.0 + LCD combination. The 800 MHz CPU runs Java/HTML5 scanner-decoding frameworks (e.g., ZXing), image-processing pipelines, and Wi-Fi/Bluetooth connectivity stacks via USB. The 24-bit LCD controller drives 320x240 to 1024x600 sunlight-readable displays. The industrial -40C to +105C temperature range suits warehouse and field deployment. Per TI's mobile-POS reference design, the AM3357 powers POS terminals, handheld scanners, and warehouse picking carts with battery-monitoring via ADC and low-power deep-sleep modes.
推荐
Industrial IoT Edge Gateway
The AM3357BZCZA80 serves as the Linux brain of industrial IoT edge gateways, aggregating fieldbus data from Modbus TCP, EtherNet/IP, PROFINET, and BACnet via the dual GbE ports and PRU-ICSS. The AES/SHA crypto accelerators secure MQTT/TLS traffic to cloud brokers (AWS IoT, Azure IoT Hub) while the Cortex-A8 runs containerized edge analytics via Docker or balenaOS. Per TI's IoT gateway reference design, the part supports local decision-making, store-and-forward buffering, and over-the-air firmware updates. The dual USB 2.0 ports accommodate cellular modems (LTE-M, NB-IoT) for sites lacking fixed connectivity.
推荐
Building Automation Controller
In BACnet/Modbus building-automation controllers, the AM3357BZCZA80 runs Niagara Framework, Sedona Framework, or open-source BACnet stacks with the Cortex-A8, while the PRU-ICSS offloads RS-485 timing-critical Modbus RTU or BACnet MS/TP polling. The dual GbE enables BACnet/IP routing with MSTP trunk redundancy. Per TI's building-automation reference design, the AM3357's industrial temperature grade and 15-year longevity program make it suitable for rooftop and basement controller installations. The CAN ports support DALI-2 lighting bus integration via gateway bridges.
推荐
推荐产品汇总
工程参考数据： AM3357BZCZA80 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AM3358BZCZA80 | AM3354BZCZA80 | AM3356BZCZA80 | AM3359BZCZA80 | AM3352BZCZ80 |
|---|---|---|---|---|---|---|
| Package | NFBGA-324 (15x15) | NFBGA-324 (15x15) - same | NFBGA-324 (15x15) - same | NFBGA-324 (15x15) - same | NFBGA-324 (15x15) - same | NFBGA-324 (15x15) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| CPU Frequency | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 600 MHz |
| 3D GPU (SGX530) | Yes | Yes | No | No | Yes | No |
| PRU-ICSS Instances | 2 | 2 | 1 | 2 | 2 | 0 |
| Cortex-M3 Wakeup MCU | No | Yes | No | No | Yes | No |
| LCD Controllers | 1 | 1 | 1 | 1 | 2 | 1 |
| Camera Interface | No | Yes | No | No | Yes | No |
关键差异点
- Integrated PRU-ICSS dual-core for industrial protocols （对比 AM3354BZCZA80)
- 3D graphics accelerator SGX530 （对比 AM3356BZCZA80)
- Industrial temperature grade -40C to +105C （对比 AM3352BZCZ80)
设计说明
Estimated: BGA escape routing for the 0.8 mm pitch NFBGA-324 requires a 4-layer or 6-layer PCB stack-up. Per TI's AM335x Hardware Design Guide (SPRABI1), signal layers should be referenced to a continuous GND plane beneath the BGA, with microvias (8-10 mil pads, 4 mil drill) used for inner-row breakout. Power traces for VDD_CORE (1+ amp at full load) need a minimum 0.5 mm width to avoid voltage droop; place 10uF X5R ceramic decaps within 5 mm of every VDD_MPU pin pair.
Per TI's TPS65086 PMIC reference design, the AM3357BZCZA80 requires sequenced power-up: VDD_CORE must rise first to 1.1 V nominal before VDDS_DDR (1.8 V) and VDDSHV (3.3 V I/O). The PMIC's PG (power-good) signal feeds RESETn; failure to sequence correctly can latch-up or damage the die. Add a 32.768 kHz external crystal on the RTC_XTAL pins for low-power deep-sleep wake-up, and reserve a 1.0 uF bulk cap near the VDD_MPU pin cluster.
The SYSBOOT[15:0] pins are sampled at PORz rising edge to select boot source, peripheral pin mux, and bus widths - these pins must be pulled to logic 0 or 1 with 10k resistors before RESETn rises; floating SYSBOOT pins cause unpredictable boot behavior. DDR3L memory should use fly-by topology with matched-length traces per the AM335x TRM; length-matched clock to data must be within 25 mil to avoid training failures in DDR PHY. The JTAG TDI/TDO chain must include the recommended 4.7k pull-ups on TCK return-path or boundary-scan may fail intermittently.
合规信息
RoHS and REACH compliant per TI product page. AEC-Q100 not qualified - use AM335x-AECQ100 variants for automotive. Lead-free / halogen-free per TI environmental declaration.
