AOZ98252QI - 8-Phase Dual-Rail Buck Controller | AOS
料号： AOZ98252QI ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
AOZ98252QI 概述
直接替换替代料： AOZ98252QI ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
AOZ98252QI-001
✅ 直接替换📋 参考替代料（不在目录中）
AOZ98252QI-000
✅ 直接替换📋 参考替代料（不在目录中）
AOZ98252QI-621
✅ 直接替换📋 参考替代料（不在目录中）
[DATA_NEEDED: verified same-package drop-in alternative]
✅ 直接替换📋 参考替代料（不在目录中）
[DATA_NEEDED: verified cross-brand drop-in alternative]
✅ 直接替换📋 参考替代料（不在目录中）
AOZ98252QI 最大额定值与电气特性
| Product Type | Digital multiphase buck controller |
| Output Rails | 2 |
| Phase Configuration | M+N = 8 phases |
| VR1 Phase Range | 0 to 8 phases |
| VR2 Phase Range | 0 to 4 phases |
| 静态电流 | 2.5 mA |
| Digital Interface | AMD SVI3 high-speed and SMBus |
| SVI Compliance | AMD SVI3 2.0 |
| Control Architecture | Variable-frequency hysteretic peak-current-mode control |
| Current Sensing | Proprietary phase-current sensing |
| Light-Load Operation | Pulse Skipping and discontinuous conduction mode |
| Phase Management | Programmable Dynamic Phase Management (DPM) |
| Transient Technology | AOS Advanced Transient Modulator (A2TM) |
| Target Applications | AMD SVI3 processors, ASICs, SoCs, and FPGAs |
| System Integration | Designed for use with external AOS DrMOS power stages |
AOZ98252QI standard 引脚配置指南
AOZ98252QI（standard 封装）的引脚配置。 该功率器件具有栅极、漏极和源极端子。对于无极性封装，请参阅制造商数据手册以了解确切的引脚 1 方向和封装尺寸细节。常见应用包括电源设计、电机驱动和负载开关。
暂无详细引脚数据： AOZ98252QI.
请参阅 数据手册 以查看完整引脚配置。
典型应用
AOZ98252QI 适用于 6 应用s: AMD SVI3 Processor Power, ASIC and SoC Multi-Rail Power, FPGA Voltage Regulation, Graphics and Desktop Power Systems, Low-Power Processor Rail Management, Digital Power-Sequencing Platform.
AMD SVI3 Processor Power
The AOZ98252QI is specifically designed for AMD SVI3 processor power systems and uses its high-speed digital interface to coordinate processor voltage regulation. Its two programmable rails and M+N=8-phase allocation allow a platform to assign more phases to a demanding core rail and fewer to an auxiliary rail. AOS identifies the controller as part of a complete solution using external DrMOS power stages. Designers should size those stages and inductors from the processor load transient specification, because the controller does not directly switch the full output current.
推荐
ASIC and SoC Multi-Rail Power
The AOZ98252QI suits ASIC and SoC platforms that require two digitally controlled output rails from one controller. VR1 can be assigned up to 8 phases, while VR2 can be assigned between 0 and 4 phases, allowing phase resources to follow rail loading. The AMD SVI3 and SMBus interfaces provide a path to system-level power-state control and telemetry. Actual implementation must confirm the ASIC voltage range, current, transient target, external power-stage timing, and the controller's complete electrical limits from the manufacturer datasheet.
推荐
FPGA Voltage Regulation
The dual-rail architecture can support FPGA systems that need coordinated high-current rails with programmable phase allocation. The controller's digital control permits system software or a platform controller to manage power states through SVI3 or SMBus-related functions. Phase count can be reduced when the load is light, improving conversion efficiency through Pulse Skipping and Dynamic Phase Management. The final design must verify the FPGA rail voltages, maximum transient current, inductor sizing, power-stage current rating, and PCB thermal capacity.
推荐
Graphics and Desktop Power Systems
AOS describes the AOZ98252QI as suitable for complete graphics and desktop power solutions built around external DrMOS devices. The controller's variable-frequency hysteretic peak-current-mode architecture and proprietary phase-current sensing are intended to support fast transient response while keeping system cost under control. Multiple phases distribute the conversion duty across external devices, but the thermal design must account for total switching loss, inductor loss, current sharing, and the physical placement of the power stages.
推荐
Low-Power Processor Rail Management
The AOZ98252QI's approximately 2.5 mA low-power operating characteristic, Pulse Skipping, and Dynamic Phase Management make it relevant to systems that spend substantial time in low-load states. During lighter operation, the controller can reduce unnecessary switching activity and use fewer active phases, while its digital interfaces permit explicit power-state control. The benefit is system dependent: standby current, transition time, inductor and power-stage losses, and the processor's own power profile must be evaluated together.
推荐
Digital Power-Sequencing Platform
The AOZ98252QI can serve as the central controller in a digitally managed power-sequencing platform for processors, ASICs, SoCs, and FPGAs. Its two rails and programmable phase allocation provide flexibility for multiple voltage domains, while SVI3 high-speed control and SMBus communication support system-level supervision. Sequencing requirements, fault responses, telemetry formats, and power-state transitions must be validated against the complete device documentation. The supplied data does not include the full register map or timing values.
推荐
推荐产品汇总
工程参考数据： AOZ98252QI ——对比、设计指导和合规信息。
选型指南
关键差异点
- Dual programmable rails in one controller （对比 AOZ98252QI-001)
- AMD SVI3 high-speed digital control （对比 AOZ98252QI-000)
- Integrated light-load efficiency features （对比 AOZ98252QI-621)
设计说明
Treat the AOZ98252QI as a digital controller and design the power path around separate external power stages. Confirm the input rail, target output voltage, maximum phase current, switching frequency, inductor ripple target, and current-sense method against the full manufacturer datasheet. Phase allocation alone does not determine output-current capability; the external DrMOS or other power-stage ratings and the inductor thermal limits set the practical ceiling.
Use the manufacturer's reference layout as the starting point for controller, current-sense, communication, bias, and power-stage placement. Keep high-current switching loops compact and isolate noisy gate-drive paths from SVI3 and SMBus traces. Verify differential-pair routing, ground references, current-sense trace geometry, and decoupling placement against the complete pinout and layout guidance, none of which were included in the supplied verified snippets.
Thermal design must include controller loss plus the selected power stages, inductors, current-sense components, and PCB copper. Phase current sharing reduces stress but does not eliminate switching loss. Use the manufacturer thermal data and the actual phase count, switching frequency, inductor DCR, and ambient temperature to estimate junction and magnetics temperature. Do not assume that a low 2.5 mA quiescent specification describes full-load controller dissipation.
Do not treat AOZ98252QI-001, AOZ98252QI-000, or AOZ98252QI-621 as interchangeable solely because distributor pages list related orderable MPNs. Verify suffix meaning, package, pinout, temperature grade, electrical limits, and interface behavior. Similarly, do not substitute a generic eight-phase controller: SVI3 protocol compatibility, SMBus behavior, current-sense implementation, gate-drive timing, and phase-allocation behavior are system-critical.
合规信息
The supplied verified data does not state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status. No compliance claim is inferred.
