CDK2307AILP64 - Dual 13-bit 20MSPS ADC | Cadeka | 64-QFN
料号： CDK2307AILP64 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
CDK2307AILP64 概述
An analog-to-digital converter (ADC) is an integrated circuit that converts continuous analog voltage signals into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. Within the broader semiconductor hierarchy, ADCs are a sub-category of data conversion ICs, which themselves fall under signal conditioning and data acquisition. As a successive-approximation or pipelined sampling ADC (per Cadeka architecture), the CDK2307 family targets mid-speed applications where power efficiency and small footprint outweigh the need for >14-bit precision or >100 MSPS conversion rates.
Key features include ultra-low power dissipation of 30 mW at 20 MSPS, an integrated bandgap reference and internal reference circuitry (eliminating the need for external reference components), digital error correction, and CMOS-compatible control and data interfaces. The 64-pin LP64 QFN package exposes a thermal pad that enables direct PCB heatsinking without external cooling hardware.
Architecturally, the CDK2307 is built on a proprietary CMOS process with a pipelined or SAR-like core (per Cadeka datasheet), one internal reference per channel pair, and a shared digital error-correction block that calibrates comparator offset on-chip. The dual-channel simultaneous-sampling capability suits applications that require correlated I/Q or stereo capture.
Typical applications include portable ultrasound front-ends, multi-channel data-acquisition boards, low-power medical imaging, communications IF/baseband digitizers, and handheld test instruments. Its low power budget also makes it suitable for battery-powered industrial sensors.
When designing with this device, follow Cadeka's recommended analog-input RC network and provide clean, low-impedance ground returns to the exposed pad. The CDK2307 is pin-compatible with the CDK2308 family (12-bit variant), allowing system reuse across resolution tiers.
This page synthesizes distributor pricing, drop-in and same-footprint alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： CDK2307AILP64 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK2307AILP64 （相同外形与封装尺寸） ——差异在于 Resolution, Manufacturer, Input Type, Package, Number of Channels.
快速对比工具——选择替代料号进行并排对比：
CDK2307BILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.28 / 个
查看数据手册 →CDK2307CILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.41 / 个
查看数据手册 →CDK2307DILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$10.4 / 个
查看数据手册 →CDK2308AILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$7.2 / 个
查看数据手册 →CDK2307AILP64X
✅ 直接替换📋 参考替代料（不在目录中）
CDK2307AILP64 最大额定值与电气特性
| Manufacturer | Cadeka Microcircuits (MaxLinear) |
| Part Number | CDK2307AILP64 |
| Description | Dual 12/13-bit 20/40/65/80 MSPS Analog-to-Digital Converter |
| 分辨率 | 13 bit (12-bit option via CDK2308 family) |
| Sampling Rate (this variant) | 20 MSPS |
| Sampling Rate (family max) | 80 MSPS (CDK2307AILP64 = 20 MSPS grade) |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Input Type | Single-ended analog input |
| Output Interface | Parallel CMOS |
| Core Supply Voltage | 1.8 V |
| I/O Supply Voltage | 1.7 V to 3.6 V |
| Power Dissipation | 30 mW at 20 MSPS; 55/85/102 mW at 40/65/80 MSPS |
| Reference | Internal (bandgap, integrated) |
| 封装 | 64-pin QFN (LP64) with exposed pad, 9x9 mm |
| 安装类型 | Surface Mount |
| Pin Compatibility | Pin-compatible with CDK2308 family (12-bit variant) |
| RoHS 状态 | Compliant |
CDK2307AILP64 64-pin qfn (lp64) with exposed pad, 9x9 mm 引脚配置指南
CDK2307AILP64（64-pin qfn (lp64) with exposed pad, 9x9 mm 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： CDK2307AILP64.
请参阅 数据手册 以查看完整引脚配置。
典型应用
CDK2307AILP64 适用于 6 应用s: Portable Ultrasound Front-End, Multi-Channel Data Acquisition Board, Communications IF/Baseband Digitizer, Handheld Test & Measurement Instrument, Low-Power Medical Imaging Subsystem, Battery-Powered Industrial Sensor Node.
Portable Ultrasound Front-End
The CDK2307AILP64's 13-bit resolution and dual-channel simultaneous sampling make it well suited for portable ultrasound beamformer front-ends. Each channel captures a transducer echo channel, and the simultaneous-sampling architecture eliminates inter-channel skew that would otherwise corrupt beam-steering calculations. At 20 MSPS the converter handles up to 10 MHz analog input bandwidth, sufficient for mid-frequency ultrasound probes (2-10 MHz). The 30 mW power dissipation at 20 MSPS supports battery-powered handheld designs without aggressive thermal management. The 64-pin LP64 QFN package keeps PCB area minimal for compact probe-handle electronics.
推荐
Multi-Channel Data Acquisition Board
Industrial data-acquisition boards requiring simultaneous multi-channel digitizing benefit from the CDK2307AILP64's dual-channel architecture. Two ADCs can be paralleled (4 channels per board section) with shared clock distribution to expand channel count while maintaining tight synchronization. The 13-bit resolution delivers 78 dB theoretical SNR (6.02 N + 1.76), adequate for vibration analysis, strain gauge digitization, and process-control feedback loops. Internal reference circuitry eliminates external reference components, reducing BOM cost. The parallel CMOS output interfaces directly with FPGA capture FIFOs at 20 MSPS without serialization overhead.
推荐
Communications IF/Baseband Digitizer
Software-defined radio (SDR) baseband receivers use the CDK2307AILP64 to digitize I/Q IF signals at up to 10 MHz bandwidth. The dual-channel simultaneous sampling captures I and Q paths with matched gain and phase response, which is essential for quadrature demodulation accuracy. The 1.8V core supply aligns with typical FPGA transceiver bank voltages, allowing direct CMOS output connection without level translation. Low 30 mW power dissipation enables portable SDR designs such as handheld spectrum analyzers. The internal bandgap reference maintains full-scale accuracy over the industrial temperature range.
推荐
Handheld Test & Measurement Instrument
Handheld oscilloscopes, logic analyzers, and bench multimeters use the CDK2307AILP64 to digitize analog measurement channels. The 20 MSPS rate supports 5 MHz real-time bandwidth, suitable for audio-bandwidth test instruments and basic embedded debugging tools. The 64-pin QFN LP64 package enables compact PCB layouts inside handheld enclosures. Low 30 mW power extends battery runtime for field engineers. The parallel CMOS output integrates with low-cost microcontrollers or FPGAs for display refresh and data logging.
推荐
Low-Power Medical Imaging Subsystem
Patient-monitoring equipment and bedside diagnostic devices use the CDK2307AILP64 to digitize physiological signals such as ECG, pulse oximetry, and respiration waveforms. The 13-bit resolution exceeds the 12-bit threshold required for diagnostic-grade ECG digitization (5 uV LSB). Dual-channel simultaneous sampling captures multi-lead ECG or synchronized SpO2/red/infrared channels. The 1.7V to 3.6V I/O supply range is compatible with modern low-power microcontrollers without level shifters. The internal reference reduces calibration drift and meets IEC 60601 medical device accuracy requirements when properly designed.
推荐
Battery-Powered Industrial Sensor Node
Wireless sensor nodes in industrial IoT deployments use the CDK2307AILP64 to digitize multi-modal sensor data such as vibration, temperature, and acoustic emission signals. The 30 mW power dissipation at 20 MSPS allows intermittent sampling from battery or energy-harvesting sources. Dual-channel simultaneous capture enables cross-correlation techniques that suppress common-mode noise in harsh industrial environments. The 64-pin QFN LP64 package withstands JEDEC J-STD-020 reflow profiles suitable for industrial PCB assembly. The internal reference and CMOS control interface minimize external component count for cost-sensitive sensor nodes.
推荐
推荐产品汇总
工程参考数据： CDK2307AILP64 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK2307BILP64 | CDK2307CILP64 | CDK2307DILP64 | CDK2308AILP64 | CDK2307AILP64X |
|---|---|---|---|---|---|---|
| Brand | Cadeka (MaxLinear) | Cadeka | Cadeka | Cadeka | Cadeka | Cadeka |
| Package | 64-pin QFN (LP64) | 64-pin QFN (LP64) - same | 64-pin QFN (LP64) - same | 64-pin QFN (LP64) - same | 64-pin QFN (LP64) - same | 64-pin QFN (LP64) - same |
| Resolution | 13 bit | 13 bit | 13 bit | 13 bit | 12 bit | 13 bit |
| Sampling Rate | 20 MSPS | 40 MSPS | 65 MSPS | 80 MSPS | 20 MSPS | 20 MSPS |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Power Dissipation | 30 mW | 55 mW | 85 mW | 102 mW | 30 mW | 30 mW |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Pin Compatibility | Pin-compatible with CDK2308 family | Same family | Same family | Same family | Same family | Same family |
关键差异点
- 20 MSPS speed grade optimizes power at low sampling rates （对比 CDK2307DILP64 (80 MSPS grade))
- Dual-channel simultaneous sampling in single package （对比 Single-channel ADS8401 (TI) in HTQFP-48)
- Pin-compatible with 12-bit CDK2308 family （对比 CDK2308AILP64)
设计说明
The CDK2307AILP64 requires a clean 1.8V core supply and a separate 1.7V to 3.6V I/O supply. Decouple each supply pin with a 100 nF ceramic capacitor placed within 3 mm of the pin, and add a bulk 10 uF tantalum or ceramic capacitor near the package. Separate analog and digital ground planes should join at a single point near the exposed thermal pad. Estimated: total supply current at 20 MSPS is approximately 17 mA from the 1.8V rail.
Solder the exposed thermal pad of the LP64 QFN package to a continuous ground plane with at least 25 thermal vias (0.3 mm drill) to inner ground layers. This keeps junction temperature rise well below 20 C at 30 mW dissipation. Without adequate pad soldering, the package thermal resistance can exceed 50 C/W, risking performance drift. Use JEDEC J-STD-020 reflow profile with peak temperature 260 C for lead-free assembly.
Route analog inputs as 50 ohm microstrip or stripline with ground-side reference, keeping traces short and away from digital output buses. Place a common-mode bypass capacitor at each analog input pin. The clock input is sensitive to jitter; use a clean low-jitter clock source and place the clock trace away from switching signals. Keep the input RC network recommended in the datasheet typical application circuit to maintain ADC SNR.
Do not exceed the maximum analog input voltage range specified in the datasheet; over-driving the input can permanently damage the converter. Ensure the I/O supply voltage matches the logic level of the receiving FPGA or ASIC to avoid CMOS latch-up. The internal reference requires a power-on settling time before valid conversions; consult the datasheet timing diagram for the tREF specification. Do not share the analog and digital ground returns under the ADC.
合规信息
RoHS and lead-free compliance confirmed via Cadeka product page and DigiKey listing. AEC-Q100 automotive qualification not documented; choose a Q1-qualified alternative for automotive designs. Halogen-free and conflict-minerals status not stated in verified web data.
