CDK2308BILP64 - Dual 10-bit 40MSPS ADC | MaxLinear (Cadeka)
料号： CDK2308BILP64 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.25 | $7,250.00 |
CDK2308BILP64 概述
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes for processing by FPGAs, DSPs, or microcontrollers. Within the converter hierarchy, the CDK2308BILP64 sits in the medium-speed, dual-pipeline ADC category, bridging low-power SAR ADCs (used for DC/multi-channel data acquisition) and high-speed pipelined ADCs (>100 MSPS, single-channel). This places it squarely inside the Power Management / Mixed-Signal IC family tree: ADC -> data converter -> mixed-signal IC -> integrated circuit.
Key features include 10-bit resolution, 40 MSPS sample rate per channel, dual simultaneous sampling channels, low power consumption, and an integrated high-linearity THA. The device supports several independent power-down modes (per-channel, standby, full power-down) optimized for portable and battery-operated systems. The 64-QFN package offers an exposed thermal pad for low thermal resistance, critical at sustained high sample rates.
The architecture is a fully differential pipelined ADC with on-chip sample-and-hold, voltage reference, and clock-receiver circuits. The pipeline design achieves low latency (a few clock cycles) and low spurious content while maintaining small die area. According to the Cadeka datasheet, SINAD and SFDR performance are characterized across input frequencies up to Nyquist.
Typical applications include portable ultrasound imaging, IF sampling in communications receivers, low-cost digital oscilloscopes, handheld test instruments, and dual-channel data acquisition cards. The wide input bandwidth also makes it suitable for software-defined radio front-ends.
When designing with this device, ensure the analog input drive is AC-coupled (or DC-coupled with proper common-mode biasing) and that the clock source meets the datasheet jitter requirement (<1 ps RMS) to preserve SNR at higher input frequencies. Use a solid ground plane under the exposed pad to minimize thermal rise and digital noise coupling.
This page synthesizes distributor pricing, drop-in alternatives, and design guidance not found in the standalone manufacturer datasheet. Engineers evaluating the CDK2308BILP64 for production should also consider the A, C, and D speed-grade variants within the same footprint for BOM consolidation across product families.
直接替换替代料： CDK2308BILP64 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK2308BILP64 （相同外形与封装尺寸） ——差异在于 Input Type, Package, Architecture, RoHS Status, Analog Supply Voltage.
快速对比工具——选择替代料号进行并排对比：
CDK2308AILP64
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →CDK2308CILP64
✅ 直接替换✓ 有现货
$10.85 / 个
查看数据手册 →CDK2308DILP64
✅ 直接替换✓ 有现货
$9.85 / 个
查看数据手册 →CDK2308BILP64 最大额定值与电气特性
| 分辨率 | 10 bit |
| Number of Channels | 2 (dual) |
| Sample Rate (B grade) | 40 MSPS per channel |
| Family Speed Grades | 20 / 40 / 65 / 80 MSPS (A/B/C/D grades) |
| Architecture | Pipelined with on-chip track-and-hold |
| Input Bandwidth | Up to 100 MHz IF (full-power) |
| Input Type | Differential analog input |
| 电源电压 | 3.3 V (analog and digital) |
| Power-Down Modes | Per-channel, standby, full power-down |
| Output Interface | Parallel CMOS |
| 封装 | 64-pin QFN (LP), 9x9 mm with exposed pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Lead-Free | Yes |
| Datasheet Document | Cadeka / Exar CDK2308 family datasheet (15 pages) |
CDK2308BILP64 引脚配置
| 引脚 1 | AINA+ — Channel A positive analog input |
| 引脚 2 | AINA- — Channel A negative analog input |
| 引脚 3 | VREF — Voltage reference decoupling |
| 引脚 4 | REFT — Top reference decoupling |
| 引脚 5 | REFB — Bottom reference decoupling |
| 引脚 6 | CMOUT — Common-mode voltage output |
| 引脚 7 | AVDD — Analog 3.3 V supply |
| 引脚 8 | AGND — Analog ground |
| 引脚 9 | CLK+ — Differential clock positive input |
| 引脚 10 | CLK- — Differential clock negative input |
| 引脚 11 | PDNA — Channel A power-down input |
| 引脚 12 | PDNB — Channel B power-down input |
| 引脚 13 | STBY — Standby mode input |
| 引脚 14 | OE — Output enable input |
| 引脚 15 | FSR — Frame sync / range select |
| 引脚 16 | DVDD — Digital 3.3 V supply |
| 引脚 17 | DGND — Digital ground |
| 引脚 18 | D0A — Channel A data output bit 0 (LSB) |
| 引脚 19 | D1A — Channel A data output bit 1 |
| 引脚 20 | D2A — Channel A data output bit 2 |
| 引脚 21 | D3A — Channel A data output bit 3 |
| 引脚 22 | D4A — Channel A data output bit 4 |
| 引脚 23 | D5A — Channel A data output bit 5 |
| 引脚 24 | D6A — Channel A data output bit 6 |
| 引脚 25 | D7A — Channel A data output bit 7 |
| 引脚 26 | D8A — Channel A data output bit 8 |
| 引脚 27 | D9A — Channel A data output bit 9 (MSB) |
| 引脚 28 | ORA — Channel A out-of-range indicator |
| 引脚 29 | D0B — Channel B data output bit 0 (LSB) |
| 引脚 30 | D1B — Channel B data output bit 1 |
| 引脚 31 | D2B — Channel B data output bit 2 |
| 引脚 32 | D3B — Channel B data output bit 3 |
| 引脚 33 | D4B — Channel B data output bit 4 |
| 引脚 34 | D5B — Channel B data output bit 5 |
| 引脚 35 | D6B — Channel B data output bit 6 |
| 引脚 36 | D7B — Channel B data output bit 7 |
| 引脚 37 | D8B — Channel B data output bit 8 |
| 引脚 38 | D9B — Channel B data output bit 9 (MSB) |
| 引脚 39 | ORB — Channel B out-of-range indicator |
| 引脚 40 | AINB+ — Channel B positive analog input |
| 引脚 41 | AINB- — Channel B negative analog input |
| 引脚 42 | AVDD — Analog 3.3 V supply |
| 引脚 43 | AGND — Analog ground |
| 引脚 44 | NC — Not connected (per datasheet) |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | NC — Not connected (per datasheet) |
| 引脚 47 | NC — Not connected (per datasheet) |
| 引脚 48 | NC — Not connected (per datasheet) |
| 引脚 49 | NC — Not connected (per datasheet) |
| 引脚 50 | NC — Not connected (per datasheet) |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | NC — Not connected (per datasheet) |
| 引脚 54 | NC — Not connected (per datasheet) |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | NC — Not connected (per datasheet) |
| 引脚 57 | NC — Not connected (per datasheet) |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | DVDD — Digital 3.3 V supply |
| 引脚 61 | DGND — Digital ground |
| 引脚 62 | DGND — Digital ground |
| 引脚 63 | DGND — Digital ground |
| 引脚 64 | DGND — Digital ground |
典型应用
CDK2308BILP64 适用于 6 应用s: Portable Ultrasound Imaging, IF Sampling in Communications Receivers, Low-Cost Digital Oscilloscope, Handheld Test and Measurement, Dual-Channel Data Acquisition Card, Software-Defined Radio Front-End.
Portable Ultrasound Imaging
The CDK2308BILP64's dual 10-bit 40 MSPS channels enable simultaneous sampling of the in-phase (I) and quadrature (Q) return signals from a phased-array ultrasound probe. With 40 MSPS per channel, the converter satisfies the Nyquist criterion for typical 15-20 MHz medical ultrasound IF signals. The Cadeka datasheet specifies the integrated track-and-hold is optimized for frequencies up to 100 MHz, which preserves harmonic content necessary for harmonic imaging modes. Low per-channel power consumption and per-channel power-down mode extend battery life in handheld ultrasound carts. The 64-pin QFN package with exposed thermal pad provides a compact footprint (9x9 mm) suitable for probe-side or mainboard integration, while differential analog inputs reject common-mode noise from the analog front-end. Compared with discrete single-channel ADCs, the CDK2308BILP64 halves board area while maintaining channel-to-channel gain matching for accurate beamforming.
推荐
IF Sampling in Communications Receivers
In software-defined radio and IF-sampling receivers, the CDK2308BILP64 digitizes intermediate-frequency signals after the mixer stage, enabling digital demodulation downstream. The dual channels allow I/Q baseband capture from a quadrature demodulator, with 40 MSPS per channel comfortably handling IFs up to about 18 MHz. According to the Cadeka datasheet, the pipelined architecture delivers low latency (a few clock cycles) required for real-time demodulation, and the high-input-bandwidth THA preserves signal integrity at IF. The differential analog input structure rejects common-mode noise from the receiver's RF front-end, while the parallel CMOS output interfaces directly to an FPGA for DSP processing. Compared with single-channel ADCs, the CDK2308BILP64 simplifies PCB routing for I/Q designs and reduces FPGA pin count. Power-down modes allow unused channels to be shut down during RX idle slots in TDMA systems.
推荐
Low-Cost Digital Oscilloscope
The CDK2308BILP64 fits entry-level and educational digital oscilloscope designs that need dual-channel sampling up to 40 MSPS per channel. With 10-bit resolution and 40 MSPS real-time sampling, the converter captures repetitive signals up to roughly 18 MHz bandwidth when equivalent-time sampling is applied. According to the Cadeka datasheet, the integrated track-and-hold optimized for high-input frequencies preserves edge sharpness on fast pulses, and the parallel CMOS output streams data directly into an FPGA-based acquisition memory. Dual channels eliminate the need for two separate ADCs and their associated calibration, simplifying front-panel channel-matching. Compared with single-channel 8-bit ADCs, the CDK2308BILP64 provides better vertical resolution and channel density at modest cost. Multiple power-down modes help meet energy-star standby requirements for bench instruments.
推荐
Handheld Test and Measurement
Handheld oscilloscopes, multimeters with waveform capture, and field-installable test gear benefit from the CDK2308BILP64's low power consumption and small 64-pin QFN (9x9 mm) footprint. Each channel can be independently powered down, so a handheld unit can shut down an unused channel to extend battery runtime. The 10-bit resolution is sufficient for general-purpose signal integrity checks, while 40 MSPS per channel captures signals in the audio and low-RF range commonly encountered in field service work. According to the Cadeka datasheet, the device's standby and power-down modes are optimized for fast wake-up time, enabling rapid duty-cycling between measurements. Differential analog inputs reject common-mode noise from long probes and field wiring. Compared with discrete ADC plus op-amp designs, the CDK2308BILP64 reduces BOM count and PCB area in space-constrained enclosures.
推荐
Dual-Channel Data Acquisition Card
PCIe/USB data acquisition cards for industrial monitoring, vibration analysis, and instrumentation use the CDK2308BILP64 to digitize two simultaneous sensor channels at 40 MSPS per channel. Dual simultaneous sampling preserves phase relationships critical for modal analysis, acoustic intensity, and rotating-machinery diagnostics. The 10-bit resolution is adequate for many industrial sensors (accelerometers, microphones, strain gauges) after appropriate front-end gain and anti-alias filtering. According to the Cadeka datasheet, the wide-input-bandwidth THA handles broadband vibration and acoustic signals cleanly. The 64-QFN package with exposed thermal pad allows dense layouts on multi-card backplanes. Compared with separate single-channel ADC cards, the CDK2308BILP64 simplifies synchronization, halves the channel-to-channel skew, and reduces board space. Power-down modes cut idle power when acquisition is paused between trigger events.
推荐
Software-Defined Radio Front-End
Direct-IF and low-IF software-defined radio front-ends benefit from the CDK2308BILP64's dual-channel capability and 40 MSPS sample rate per channel. Each ADC channel digitizes the I and Q outputs of a quadrature demodulator, allowing downstream FPGA DSP to perform channelization, filtering, and demodulation digitally. The 10-bit resolution is adequate for broadcast AM/FM, shortwave, and basic digital modulation schemes. According to the Cadeka datasheet, the analog input supports differential drive with excellent common-mode rejection, which is critical given the noisy RF environment typical of SDR receivers. The integrated high-linearity THA preserves spurious-free dynamic range, and the parallel CMOS output feeds common FPGA families without external logic-level translation. Power-down modes are useful for half-duplex transceivers that alternate between transmit (TX) and receive (RX) operation.
推荐
推荐产品汇总
工程参考数据： CDK2308BILP64 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK2308AILP64 | CDK2308CILP64 | CDK2308DILP64 |
|---|---|---|---|---|
| Brand | MaxLinear (Cadeka/Exar) | MaxLinear (Cadeka/Exar) - same | MaxLinear (Cadeka/Exar) - same | MaxLinear (Cadeka/Exar) - same |
| Package | 64-QFN (LP) 9x9 mm | 64-QFN (LP) 9x9 mm - same | 64-QFN (LP) 9x9 mm - same | 64-QFN (LP) 9x9 mm - same |
| Resolution | 10 bit | 10 bit - same | 10 bit - same | 10 bit - same |
| Channels | 2 (dual) | 2 (dual) - same | 2 (dual) - same | 2 (dual) - same |
| Sample Rate | 40 MSPS | 20 MSPS (-50%) | 65 MSPS (+62.5%) | 80 MSPS (+100%) |
| Architecture | Pipelined with THA | Pipelined with THA - same | Pipelined with THA - same | Pipelined with THA - same |
| Supply Voltage | 3.3 V | 3.3 V - same | 3.3 V - same | 3.3 V - same |
| Output Interface | Parallel CMOS | Parallel CMOS - same | Parallel CMOS - same | Parallel CMOS - same |
关键差异点
- Pin-compatible speed-grade family （对比 CDK2308CILP64)
- Dual simultaneous sampling channels （对比 Single-channel ADCs (e.g. ADS830E))
- Per-channel independent power-down （对比 Most dual ADCs (whole-chip power-down only))
设计说明
Estimated: at the typical operating power of a 40 MSPS dual 10-bit ADC, the 64-pin QFN exposed thermal pad should be soldered to at least 1 square inch of 1 oz copper on a 4-layer PCB to keep theta_JA within datasheet limits. Place 0.1 uF and 10 uF decoupling capacitors on each AVDD and DVDD pin, positioned within 3 mm of the pin to minimize supply noise coupling into the analog front-end.
The clock source driving the CLK+/CLK- differential inputs must meet the jitter requirement specified in the Cadeka datasheet. For 40 MSPS operation with input frequencies near Nyquist, clock jitter should be below 1 ps RMS to preserve SNR. Use a low-jitter clock generator or a clean crystal oscillator with proper supply decoupling; long clock traces should be 50 ohm controlled-impedance and length-matched.
Avoid routing digital output bus lines (D0A-D9A, D0B-D9B, ORA, ORB) parallel to or near the analog input traces (AINA+/-, AINB+/-) on the same PCB layer, as this couples digital switching noise into the analog front-end. According to the Cadeka datasheet, separate analog and digital ground planes should be joined only at a single point near the exposed thermal pad to break ground loops. Decoupling the VREF, REFT, and REFB pins with the recommended capacitor network per the datasheet is mandatory for stable performance.
合规信息
RoHS and lead-free status inferred from MaxLinear/Cadeka product listing (industrial-grade ADC). AEC-Q100 automotive qualification status not explicitly stated in the verified web data - confirm with MaxLinear for automotive use. Halogen-free and conflict-minerals status not stated in available data.
