DS90C031TMX - 155.5Mbps Quad LVDS Driver | Texas Instruments
料号： DS90C031TMX ✗ 停产DS90C031TMX 概述
An LVDS line driver is a differential interface device that converts single-ended logic signals into two complementary low-voltage outputs. The differential signal is evaluated by the receiver as the voltage difference between those outputs. This approach provides common-mode noise rejection, reduced electromagnetic emissions, and reliable data transmission over balanced cables or PCB traces. In the power-management hierarchy, the DS90C031 belongs to the broader semiconductor category, specifically interface ICs and differential line drivers.
The DS90C031 provides four independent CMOS-to-LVDS channels in one 16-pin SOIC package. Its specified data rate exceeds 155.5 Mbps, corresponding to a 77.7 MHz parallel word-transfer rate. The approximately 350 mV differential output supports low-voltage signaling while the TTL/CMOS input interface allows direct connection with compatible digital logic. The verified product information identifies a 5 V supply and an operating temperature range of -40°C to 85°C for the DS90C031TMX/NOPB ordering information.
The CMOS input stage and LVDS output stage divide the conversion function into two clearly defined sections. Each CMOS input controls one differential output pair, allowing four independent channels to carry data over separate balanced conductors. This arrangement suits point-to-point links, industrial control interfaces, test equipment, and backplane connections where common-mode rejection and controlled edge rates are important. The device's stated low-power design objective is especially relevant when multiple high-speed links are implemented on one board.
Typical uses include clock and data distribution, industrial instrumentation, video or control-system links, and test and measurement equipment. Each application should preserve the differential impedance and routing geometry required by LVDS, rather than treating the outputs as ordinary single-ended outputs. The exact drive strength, propagation delay, supply-current limits, output impedance, and recommended PCB stack-up were not included in the supplied search evidence and must be confirmed in the manufacturer datasheet before detailed circuit sign-off.
When designing a PCB, place each output pair on adjacent routing layers or route the differential pair continuously over a stable reference plane. Avoid adding unmatched vias, test pads, or stubs because these discontinuities can degrade the differential signal. Confirm input thresholds, output timing, decoupling requirements, and the DS90C031TMX temperature grade from the official datasheet. Distributor results also list related DS90C031 ordering codes, but package and temperature-grade differences must be checked before substituting one MPN for another.
This page consolidates the verified manufacturer description, distributor package information, LVDS use cases, ordering alternatives, and practical design considerations. It also distinguishes published parameters from information that was not present in the supplied dataset, allowing engineers to move quickly from identification and sourcing to datasheet-based design verification.
直接替换替代料： DS90C031TMX ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DS90C031TMX （相同外形与封装尺寸） ——差异在于 Differential Output Voltage, Package.
DS90C031BTM
✅ 直接替换联系询价
查看数据手册 →DS90C031TMX 规格参数
| Product Type | Quad CMOS differential line driver |
| Interface Standard | Low Voltage Differential Signaling (LVDS) |
| Number of Channels | 4 channels |
| Input Logic Compatibility | TTL/CMOS |
| Maximum Data Rate | In excess of 155.5 Mbps |
| Equivalent Parallel Data Rate | 77.7 MHz |
| Differential Output Voltage | Approximately 350 mV |
| 电源电压 | 5 V |
| 工作温度 | -40°C to +85°C |
| 封装 | 16-pin SOIC |
| 安装类型 | Surface mount |
| Technology | CMOS |
| Device Type | Line / bus driver |
| Driver Direction | 4 inputs / 0 differential outputs |
| Input Signal | Single-ended TTL/CMOS |
| Output Signal | Low-voltage differential |
| RoHS Compliance | unknown |
| REACH Compliance | unknown |
DS90C031TMX 16-pin soic 引脚配置指南
DS90C031TMX（16-pin soic 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： DS90C031TMX.
请参阅 数据手册 以查看完整引脚配置。
典型应用
DS90C031TMX 适用于 6 应用s: Industrial Control Signal Distribution, Test and Measurement Data Links, Clock Distribution, Instrumentation Backplane Communication, High-Speed Digital Interface Bridging, Video and Control Signal Distribution.
Industrial Control Signal Distribution
The DS90C031TMX fits point-to-point industrial control links that require four balanced LVDS outputs at rates in excess of 155.5 Mbps. Each TTL/CMOS input can feed a separate differential channel, reducing the number of driver packages needed when distributing commands, timing signals, or sensor data across a cabinet. According to the Texas Instruments product description, the approximately 350 mV differential output and low-power design objective suit compact control boards. The implementation should preserve a continuous differential trace over a continuous reference plane, minimize unmatched stubs, and verify noise-margin and common-mode limits against the selected receiver. Because the supplied evidence does not specify isolation, surge level, or industrial certification, those requirements must be handled elsewhere in the interface or confirmed from the full manufacturer datasheet.
推荐
Test and Measurement Data Links
The DS90C031TMX is appropriate for high-speed data paths in test and measurement equipment where four parallel channels must be converted from TTL/CMOS logic into balanced LVDS signals. Its verified rate above 155.5 Mbps, equivalent to 77.7 MHz for parallel transfer, provides useful margin for clock, trigger, and digitized-result links. The differential output helps reject common-mode noise encountered near switching converters, digital processors, and relay or driver circuitry. For a practical design, route each positive and negative output as a tightly coupled pair and keep return-current paths continuous. Confirm propagation delay, output impedance, skew, and receive thresholds from the manufacturer datasheet because those timing details were not present in the supplied search evidence.
推荐
Clock Distribution
The four-channel architecture of the DS90C031TMX supports independent clock distribution where a backplane, instrument, or controller requires several low-voltage differential clock outputs. The verified 155.5 Mbps capability and approximately 350 mV differential amplitude align with the device's stated LVDS signaling method, while the TTL/CMOS input stage can accept compatible logic. Clock integrity still depends on the receiver's input bandwidth and the source's duty-cycle and jitter behavior, so the datasheet timing specifications must be checked before fanout or cable use. On the PCB, use symmetric routing and identical termination practices across channels, avoid changing reference planes beneath a differential pair, and keep test access structures electrically equivalent across all four outputs.
推荐
Instrumentation Backplane Communication
The DS90C031TMX can support balanced data links between instrumentation modules when low emissions, noise immunity, and multi-channel throughput are priorities. Its four LVDS outputs allow several point-to-point paths to be implemented without using four separate single-ended driver packages. According to the verified Texas Instruments description, the device accepts TTL/CMOS inputs and exceeds 155.5 Mbps while maintaining a low-voltage differential output. Practical deployment requires a receiver with compatible thresholds and termination, controlled differential impedance, and verification of cable attenuation over the intended length. The available evidence does not include input capacitance, output impedance, or skew limits, so those parameters must be obtained from the official manufacturer datasheet before sign-off.
推荐
High-Speed Digital Interface Bridging
The DS90C031TMX is useful when a controller, FPGA interface, or digital subsystem must launch four balanced signals onto a board-to-board or short-cable connection. The verified 155.5 Mbps data-rate capability provides a practical path for command, status, or parallel data transfer, and the 5 V supply requirement allows integration with established industrial and instrumentation power systems. Designers should treat the output as a controlled differential edge rather than a general-purpose CMOS output. Maintain matched impedance, minimize connector and via transitions, and validate inter-pair skew and receiver recovery behavior at the highest intended rate. Exact timing and drive-strength information is unavailable in the supplied excerpts and must be checked in the manufacturer datasheet.
推荐
Video and Control Signal Distribution
The DS90C031TMX can distribute low-voltage differential control or ancillary signals where multiple balanced outputs are needed and the link operates below the device's verified 155.5 Mbps capability. Its approximately 350 mV output and differential signaling reduce sensitivity to common-mode noise compared with ordinary single-ended routing, which can help in equipment containing switching power stages and digital processors. The four-channel implementation simplifies board partitioning by carrying several related signals in one 16-pin SOIC. Video-specific requirements still need separate review: the component is a general LVDS line driver rather than a documented video transmitter. Confirm input levels, edge rate, termination, cable length, and any domain-specific EMC requirements before using it in a video-control subsystem.
推荐
工程参考数据： DS90C031TMX ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DS90C031BTM |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Package | 16-pin SOIC | 16-pin SOIC |
| Product Type | Quad CMOS differential line driver | LVDS interface driver |
| Supply Voltage | 5 V | 5 V |
关键差异点
- Four independent LVDS channels in one package （对比 DS90C031BTM)
- TTL/CMOS input conversion with a 350 mV differential result （对比 DS90C031BTM)
- Documented high-speed capability for four balanced links （对比 DS90C031BTM)
设计说明
Route every LVDS output as a tightly coupled differential pair with continuous reference-plane return paths. Keep the positive and negative traces on the same layer where practical, match their length and geometry, and avoid splitting the pair around other signals. The verified evidence establishes 350 mV differential signaling and rates above 155.5 Mbps, but it does not provide the manufacturer's recommended impedance or stack-up values, so those must be obtained from the full datasheet before PCB release.
Do not treat DS90C031BTM as an unconditional substitute merely because both parts are associated with a 16-pin SOIC and the DS90C031 family. The supplied comparison explicitly says that some electrical characteristics differ. Compare propagation delay, output impedance, supply-current limits, temperature range, and ordering-code markings in the manufacturer datasheets, then verify timing at the highest operating data rate before approving the replacement.
Avoid unmatched test pads, vias, and stubs on differential nets because these structures can reflect energy and reduce the usable margin at the verified 155.5 Mbps-plus signaling rate. If test access is required, use symmetric structures on both conductors and follow the receiver's termination arrangement. Also confirm source timing, propagation delay, and inter-channel skew from the official datasheet because the supplied search excerpts do not include those numerical limits.
合规信息
The supplied search results do not provide verified RoHS, REACH, lead-free, halogen-free, or conflict-minerals statements. AEC-Q100 is treated as not applicable because no automotive qualification is stated for this ordering code.