DSPIC33FJ64GP310-I/PT - 16-Bit 40MIPS 64KB DSC | Microchip
料号： DSPIC33FJ64GP310-I/PT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.32 | $8.32 |
| 10 | $7.49 | $74.90 |
| 100 | $6.65 | $665.00 |
| 500 | $6.02 | $3,010.00 |
| 1,000 | $5.48 | $5,480.00 |
DSPIC33FJ64GP310-I/PT 概述
A Digital Signal Controller (DSC) bridges the gap between a microcontroller (MCU) and a digital signal processor (DSP). Within the embedded-control hierarchy, the DSC sits above a standard PIC24 MCU and below a dedicated DSP, adding a 17-bit x 17-bit hardware multiplier, 40-bit accumulators, dual operand fetch and single-cycle MAC operations on top of a 16-bit modified Harvard core. This architecture shortens FIR/IIR filter and control-loop execution dramatically compared to software-emulated multiply on general MCUs.
Key features include 40 MIPS CPU speed at 3.0-3.6 V, 64 KB self-programmable FLASH, 16 KB RAM, in-circuit serial programming (ICSP) and debugging via any PGECx/PGEDx pin pair, plus flexible clocking with internal fast RC oscillator and PLL options that allow operation without an external crystal. The integrated high-speed ADC subsystem with multiple sample-and-hold inputs suits simultaneous motor-phase and sensor sampling.
Typical applications include digital power conversion and power-factor correction, sensorless BLDC and PMSM motor control, audio and speech signal processing, industrial sensing and instrumentation, and switch-mode power supply control, where 40 MIPS plus hardware DSP math meets tight loop-closure deadlines.
When designing with the DSPIC33FJ64GP310-I/PT, remember that it has more than one PGECx/PGEDx pin pair: any pair may be used for ICSP, but the pair must be used together (for example PGEC2 with PGED2). Confirm decoupling and trace lengths per Microchip's dsPIC33F family reference design.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： DSPIC33FJ64GP310-I/PT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DSPIC33FJ64GP310-I/PT （相同外形与封装尺寸） ——差异在于 Package, Core Architecture, Programming Interface, Series, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
DSPIC33FJ64GP310A-I/PT
✅ 直接替换✓ 有现货
$4.75 / 个
查看数据手册 →DSPIC33FJ128GP310-I/PT
✅ 直接替换✓ 有现货
$4.4 / 个
查看数据手册 →DSPIC33FJ64GP310T-I/PT
✅ 直接替换✓ 有现货
$5.78 / 个
查看数据手册 →DSPIC33FJ128GP310T-I/PF
✅ 直接替换✓ 有现货
$5.95 / 个
查看数据手册 →DSPIC33FJ256GP710A-I/PT
✅ 直接替换✓ 有现货
$15.6 / 个
查看数据手册 →DSPIC33FJ64GP706A-I/MR
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$10.1 / 个
查看数据手册 →DSPIC33FJ64GP310-I/PT 最大额定值与电气特性
| Core Architecture | dsPIC33F, 16-bit modified Harvard with DSP engine |
| CPU Speed | 40 MIPS (3.0 V to 3.6 V) |
| Program Memory (FLASH) | 64 KB (64K x 8) |
| Data RAM | 16 KB |
| Operating Voltage | 3.0 V to 3.6 V |
| 工作温度范围 | -40C to +85C (Industrial) |
| 封装 | 100-pin TQFP (12x12 mm) |
| 安装类型 | Surface Mount |
| Hardware Multiplier | 17-bit x 17-bit, single-cycle MAC |
| Accumulator | Two 40-bit |
| Programming/Debug | ICSP via PGECx/PGEDx pin pairs |
| DMA Channels | 8-channel DMA |
| ADC | High-speed 10/12-bit ADC with multiple sample-and-hold |
| RoHS 状态 | Compliant |
DSPIC33FJ64GP310-I/PT 引脚配置
| 引脚 1 | RP15/PWM3H/PMCS1/RA7 — Remappable I/O or PWM output or Peripheral Master Chip Select |
| 引脚 10 | RP2/PWM4H/SCL1/INT2/RD2 — Remappable I/O or PWM or I2C SCL or external interrupt |
| 引脚 100 | RP0/PWM4H/SDA1/INT1/RD0 — Remappable I/O or PWM or I2C SDA or external interrupt |
| 引脚 11 | RP3/PWM4L/SDA1/INT3/RD3 — Remappable I/O or PWM or I2C SDA or external interrupt |
| 引脚 12 | RP4/PWM5H/SCL1/INT4/RD4 — Remappable I/O or PWM or I2C SCL or external interrupt |
| 引脚 13 | OSCI/RA1 — External crystal oscillator input |
| 引脚 14 | OSCO/RA0 — External crystal oscillator output |
| 引脚 15 | VDD — Core supply voltage (3.0-3.6 V) |
| 引脚 16 | VSS — Ground reference |
| 引脚 17 | RP16/PMD0/RE0 — Remappable I/O or Parallel Master Data bit 0 |
| 引脚 18 | RP17/PMD1/RE1 — Remappable I/O or Parallel Master Data bit 1 |
| 引脚 19 | RP18/PMD2/RE2 — Remappable I/O or Parallel Master Data bit 2 |
| 引脚 2 | RP14/PWM3L/PMD7/RA6 — Remappable I/O or PWM or Parallel Master Data bit 7 |
| 引脚 20 | RP19/PMD3/RE3 — Remappable I/O or Parallel Master Data bit 3 |
| 引脚 21 | RP20/PMD4/RE4 — Remappable I/O or Parallel Master Data bit 4 |
| 引脚 22 | RP21/PMD5/RE5 — Remappable I/O or Parallel Master Data bit 5 |
| 引脚 23 | RP22/PMD6/RE6 — Remappable I/O or Parallel Master Data bit 6 |
| 引脚 24 | RP23/PMD7/RE7 — Remappable I/O or Parallel Master Data bit 7 |
| 引脚 25 | AVDD — Analog supply voltage (3.0-3.6 V) |
| 引脚 26 | AVSS — Analog ground reference |
| 引脚 27 | AN0/VREF+/RB0 — Analog input 0 / positive voltage reference / I/O |
| 引脚 28 | AN1/VREF-/RB1 — Analog input 1 / negative voltage reference / I/O |
| 引脚 29 | AN2/RB2 — Analog input 2 / I/O |
| 引脚 3 | RP13/PWM2H/PMD6/RA5 — Remappable I/O or PWM or Parallel Master Data bit 6 |
| 引脚 30 | AN3/RB3 — Analog input 3 / I/O |
| 引脚 31 | AN4/RB4 — Analog input 4 / I/O |
| 引脚 32 | AN5/RB5 — Analog input 5 / I/O |
| 引脚 33 | AN6/RB6 — Analog input 6 / I/O |
| 引脚 34 | AN7/RB7 — Analog input 7 / I/O |
| 引脚 35 | AN8/RB8 — Analog input 8 / I/O |
| 引脚 36 | AN9/RB9 — Analog input 9 / I/O |
| 引脚 37 | AN10/RB10 — Analog input 10 / I/O |
| 引脚 38 | AN11/RB11 — Analog input 11 / I/O |
| 引脚 39 | AN12/RB12 — Analog input 12 / I/O |
| 引脚 4 | RP12/PWM2L/PMD5/RA4 — Remappable I/O or PWM or Parallel Master Data bit 5 |
| 引脚 40 | AN13/RB13 — Analog input 13 / I/O |
| 引脚 41 | AN14/RB14 — Analog input 14 / I/O |
| 引脚 42 | AN15/OCFB/RB15 — Analog input 15 / output compare fault B / I/O |
| 引脚 43 | VDD — Core supply voltage (3.0-3.6 V) |
| 引脚 44 | VSS — Ground reference |
| 引脚 45 | RP24/RC0 — Remappable I/O |
| 引脚 46 | RP25/RC1 — Remappable I/O |
| 引脚 47 | RP26/RC2 — Remappable I/O |
| 引脚 48 | RP27/RC3 — Remappable I/O |
| 引脚 49 | RP28/RC4 — Remappable I/O |
| 引脚 5 | RP11/PWM1H/PMD4/RA3 — Remappable I/O or PWM or Parallel Master Data bit 4 |
| 引脚 50 | RP29/RC5 — Remappable I/O |
| 引脚 51 | RP30/RC6 — Remappable I/O |
| 引脚 52 | RP31/RC7 — Remappable I/O |
| 引脚 53 | RP8/PWM5H/PMD8/RF0 — Remappable I/O or PWM or Parallel Master Data bit 8 |
| 引脚 54 | RP9/PWM5L/PMD9/RF1 — Remappable I/O or PWM or Parallel Master Data bit 9 |
| 引脚 55 | RP10/PWM6H/PMD10/RF2 — Remappable I/O or PWM or Parallel Master Data bit 10 |
| 引脚 56 | RP5/PWM6L/PMD11/RF3 — Remappable I/O or PWM or Parallel Master Data bit 11 |
| 引脚 57 | RP6/PWM3H/PMD12/RF4 — Remappable I/O or PWM or Parallel Master Data bit 12 |
| 引脚 58 | RP7/PWM3L/PMD13/RF5 — Remappable I/O or PWM or Parallel Master Data bit 13 |
| 引脚 59 | MCLR — Master Clear (reset) input, active low |
| 引脚 6 | RP0/PWM1L/PMD0/RA0 — Remappable I/O or PWM or Parallel Master Data bit 0 |
| 引脚 60 | PGEC1 — ICSP clock / ICD clock (pair with PGED1) |
| 引脚 61 | PGED1 — ICSP data / ICD data (pair with PGEC1) |
| 引脚 62 | PGEC2 — ICSP clock / ICD clock (pair with PGED2) |
| 引脚 63 | PGED2 — ICSP data / ICD data (pair with PGEC2) |
| 引脚 64 | RP1/PMD0/RD1 — Remappable I/O or Parallel Master Data bit 0 |
| 引脚 65 | RP2/PMD1/RD2 — Remappable I/O or Parallel Master Data bit 1 |
| 引脚 66 | RP3/PMD2/RD3 — Remappable I/O or Parallel Master Data bit 2 |
| 引脚 67 | RP4/PMD3/RD4 — Remappable I/O or Parallel Master Data bit 3 |
| 引脚 68 | VDD — Core supply voltage (3.0-3.6 V) |
| 引脚 69 | VSS — Ground reference |
| 引脚 7 | RP1/PWM1H/PMD1/RA1 — Remappable I/O or PWM or Parallel Master Data bit 1 |
| 引脚 70 | RP8/PMD8/RF0 — Remappable I/O or Parallel Master Data bit 8 |
| 引脚 71 | RP9/PMD9/RF1 — Remappable I/O or Parallel Master Data bit 9 |
| 引脚 72 | RP10/PMD10/RF2 — Remappable I/O or Parallel Master Data bit 10 |
| 引脚 73 | RP11/PMD11/RF3 — Remappable I/O or Parallel Master Data bit 11 |
| 引脚 74 | RP12/PMD12/RF4 — Remappable I/O or Parallel Master Data bit 12 |
| 引脚 75 | RP13/PMD13/RF5 — Remappable I/O or Parallel Master Data bit 13 |
| 引脚 76 | RP14/PMD14/RF6 — Remappable I/O or Parallel Master Data bit 14 |
| 引脚 77 | RP15/PMD15/RF7 — Remappable I/O or Parallel Master Data bit 15 |
| 引脚 78 | VDD — Core supply voltage (3.0-3.6 V) |
| 引脚 79 | VSS — Ground reference |
| 引脚 8 | RP8/PWM2L/PMD8/RD0 — Remappable I/O or PWM or Parallel Master Data bit 8 |
| 引脚 80 | RA15 — General purpose I/O |
| 引脚 81 | RA14 — General purpose I/O |
| 引脚 82 | RA13 — General purpose I/O |
| 引脚 83 | RA12 — General purpose I/O |
| 引脚 84 | RA11 — General purpose I/O |
| 引脚 85 | RA10 — General purpose I/O |
| 引脚 86 | RA9 — General purpose I/O |
| 引脚 87 | RA8 — General purpose I/O |
| 引脚 88 | RA7 — General purpose I/O |
| 引脚 89 | RA6 — General purpose I/O |
| 引脚 9 | RP9/PWM2H/PMD9/RD1 — Remappable I/O or PWM or Parallel Master Data bit 9 |
| 引脚 90 | RA5 — General purpose I/O |
| 引脚 91 | RA4 — General purpose I/O |
| 引脚 92 | RA3 — General purpose I/O |
| 引脚 93 | RA2 — General purpose I/O |
| 引脚 94 | RA1 — General purpose I/O |
| 引脚 95 | RA0 — General purpose I/O |
| 引脚 96 | VDD — Core supply voltage (3.0-3.6 V) |
| 引脚 97 | VSS — Ground reference |
| 引脚 98 | RP8/PWM3H/RD0 — Remappable I/O or PWM |
| 引脚 99 | RP9/PWM3L/RD1 — Remappable I/O or PWM |
典型应用
DSPIC33FJ64GP310-I/PT 适用于 7 应用s: Sensorless BLDC Motor Control, Digital Power Conversion (PFC + LLC), Audio and Speech Signal Processing, Industrial Sensor Conditioning and Instrumentation, Switch-Mode Power Supply (SMPS) Control, Automotive Body and Comfort Modules, Consumer Appliance Control Boards.
Sensorless BLDC Motor Control
The DSPIC33FJ64GP310-I/PT is widely used for sensorless BLDC and PMSM motor drives thanks to its 40 MIPS DSP engine and high-speed ADC with multiple sample-and-hold inputs. The hardware MAC and dual 40-bit accumulators execute field-oriented control loops and zero-crossing back-EMF detection within microseconds, while the 100-pin TQFP exposes six PWMs and quadrature encoder inputs for three-phase drive. Compared to a software-only PID on a generic MCU, the dsPIC33F reduces loop-closure latency by 5-10x, enabling higher RPM and smoother torque. Paired with gate drivers like the MCP8024 and a 3-shunt current-sense stage, this DSC delivers production-grade sensorless control for fans, pumps, e-bikes, and appliance drives.
推荐
Digital Power Conversion (PFC + LLC)
In digital power supplies and power-factor correction (PFC) stages, the DSPIC33FJ64GP310-I/PT runs voltage-mode and average-current-mode control loops at switching frequencies up to several hundred kHz. Its 40 MIPS DSP engine executes CCM/DCM PFC math and LLC resonant control in a single part, while the 12-bit ADC with multiple S&H channels samples input voltage, input current, and output voltage simultaneously - critical for digital PFC per Microchip's dsPIC33F SMPS reference designs. The 64 KB FLASH accommodates state-machine plus digital compensator code. Paired with an isolated gate driver like the Si8271 or a digital-power-optimized analog front end, this DSC replaces legacy analog UCCx808 controllers with a flexible software-defined control law.
推荐
Audio and Speech Signal Processing
The DSPIC33FJ64GP310-I/PT handles audio and speech processing tasks such as FIR/IIR filtering, noise suppression, and acoustic echo cancellation directly in firmware. The hardware 17-bit x 17-bit MAC and dual 40-bit accumulators sustain sample-rate audio processing up to 48 kHz without CPU loading, while 16 KB RAM buffers several hundred audio samples per channel. The 100-pin TQFP package exposes I2S/SPT interfaces that pair with external audio CODECs like the AK4642. Compared to a generic MCU, the dsPIC33F cuts audio-filter cycles by 5x, freeing CPU headroom for higher-level DSP like FFT-based spectral processing. Common uses include intercom, hearing-aid preprocessing, and speech-recognition front ends.
推荐
Industrial Sensor Conditioning and Instrumentation
For industrial sensor conditioning and instrumentation, the DSPIC33FJ64GP310-I/PT integrates a 16-bit DSC core with 10/12-bit ADC and DSP math for strain gauge, load cell, and temperature sensor linearization. The 40 MIPS throughput executes polynomial compensation and digital filtering at high update rates, while the industrial -40C to +85C temperature rating suits factory-floor environments. The 100-pin TQFP exposes UART, SPI, and I2C for connectivity to host PLCs or HMI panels, and the 64 KB FLASH stores calibration tables alongside application firmware. Compared with a discrete op-amp + ADC solution, this DSC lowers BOM cost by integrating signal chain and MCU in one part.
推荐
Switch-Mode Power Supply (SMPS) Control
In switch-mode power supply (SMPS) control, the DSPIC33FJ64GP310-I/PT executes peak-current-mode and voltage-mode control loops for buck, boost, and flyback topologies. The DSP engine runs the digital compensator and soft-start sequencing, while high-resolution PWM and ADC synchronization enable sub-microsecond duty-cycle updates. The 64 KB FLASH and 16 KB RAM fit multi-loop firmware including telemetry and PMBus-style monitoring. Per Microchip's dsPIC33F SMPS reference design, this DSC supports 200-500 kHz switching with adequate margin. Compared to an analog UC3842 controller, it adds programmability, telemetry, and adaptive loop tuning in software.
推荐
Automotive Body and Comfort Modules
While the DSPIC33FJ64GP310-I/PT is industrial-grade, it is also widely used in non-safety automotive body and comfort modules such as HVAC blower controllers, seat heaters, mirror modules, and LED drivers. Its 40 MIPS DSP engine runs LIN/CAN-connected motor and lighting control loops, while the 100-pin TQFP exposes enough PWMs for multi-channel LED dimming and DC-motor drive. The -40C to +85C industrial temperature rating covers most cabin environments. Compared with automotive-grade AEC-Q100 DSCs (e.g. DSPIC33FJ64MC510A-I/PT), this part saves cost for non-safety modules where AEC-Q100 qualification is not required. It is a strong fit for body-electronics OEMs targeting mid-volume passenger programs.
推荐
Consumer Appliance Control Boards
The DSPIC33FJ64GP310-I/PT is a strong fit for consumer appliance control boards including washing machines, dishwashers, induction cookers, and refrigerator inverters. Its DSP engine handles BLDC motor control for variable-speed compressors and pumps, while the 100-pin TQFP exposes touch-sense, display, and user-interface peripherals. The 64 KB FLASH and 16 KB RAM accommodate state-machine firmware plus application code, and the ICSP debug port speeds up mass-production programming. Compared to a discrete MCU + motor-driver solution, this DSC reduces board area and BOM cost while supporting firmware updates across appliance model variants.
推荐
推荐产品汇总
工程参考数据： DSPIC33FJ64GP310-I/PT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DSPIC33FJ64GP310A-I/PT | DSPIC33FJ128GP310-I/PT | DSPIC33FJ64GP310T-I/PT | DSPIC33FJ128GP310T-I/PF | DSPIC33FJ256GP710A-I/PT |
|---|---|---|---|---|---|---|
| Package | TQFP-100 (12x12 mm) | TQFP-100 (12x12 mm) - same | TQFP-100 (12x12 mm) - same | TQFP-100 (12x12 mm) - same | TQFP-100 (14x14 mm) - verify land pattern | TQFP-100 (12x12 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed (MIPS) | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| FLASH Memory | 64 KB | 64 KB (same) | 128 KB (+100%) | 64 KB (same) | 128 KB (+100%) | 256 KB (+300%) |
| Data RAM | 16 KB | 16 KB (same) | 16 KB (same) | 16 KB (same) | 16 KB (same) | 32 KB (+100%) |
| Operating Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Silicon Revision / Variant | Base GP310, 64 KB | Rev A errata-fix | GP310 die with 128 KB FLASH | Tape & reel packaging code | 128 KB FLASH, T&R, 14x14 TQFP | GP710 die with 256 KB FLASH |
关键差异点
- Same silicon with errata fix in identical TQFP-100 12x12 footprint （对比 DSPIC33FJ64GP310A-I/PT)
- Doubles FLASH to 128 KB in identical TQFP-100 12x12 footprint （对比 DSPIC33FJ128GP310-I/PT)
- Same die with 256 KB FLASH + 32 KB RAM in identical TQFP-100 12x12 footprint （对比 DSPIC33FJ256GP710A-I/PT)
设计说明
The DSPIC33FJ64GP310-I/PT requires a clean 3.0 V to 3.6 V supply. Place a 10 uF bulk tantalum or ceramic capacitor near each VDD/VSS pair on the 100-pin TQFP, with a 0.1 uF ceramic decoupling cap adjacent to every VDD pin (per Microchip dsPIC33F hardware design checklist). AVDD must be tied to VDD with its own decoupling network; failure to decouple AVDD separately introduces ADC noise that exceeds the 12-bit ENOB.
Route PGECx/PGEDx pairs as short, parallel, length-matched traces (under 50 mm) and add a series 4.7 kohm pull-up on MCLR to VDD per the dsPIC33F programming specification. The 100-pin TQFP at 12x12 mm uses 0.5 mm pitch - use 0.15 mm trace/space rules with vias-in-pad if your fab supports it, otherwise dog-bone fanout. Provide a ground pour under the IC for thermal dissipation; the package is rated at roughly 1 W without airflow.
Do NOT use PGEC1 with PGED2 (or any mismatched pair) for ICSP - the dsPIC33F datasheet requires PGECx and PGEDx to use the SAME index. Also, leave unused analog inputs tied to AVSS or AVDD (not floating) to avoid shoot-through current in the ADC input mux. When migrating from dsPIC30F code, verify the interrupt vector table - the dsPIC33F uses a different IVT layout and the legacy dsPIC30F vectors will not run.
合规信息
Industrial temperature grade -40C to +85C; not AEC-Q100 qualified. RoHS and REACH compliant per Microchip product page. Lead-free and halogen-free per Microchip environmental certification.
